NXP Semiconductors SE98ATP,147

Overview

SE98ATP,147 from NXP Semiconductors is a JEDEC JC-42.4-compliant digital temperature sensor IC designed for DDR2/DDR3 memory module thermal monitoring. It delivers ±0.5 °C (typ.) accuracy between +75 °C and +95 °C, operates from 1.7 V to 3.6 V, features an open-drain EVENT output, and communicates via I²C/SMBus up to 400 kHz - deployed directly on DIMMs to protect DRAM under thermal stress.

For engineers reviewing the SE98ATP,147 datasheet, SE98ATP,147 pinout, SE98ATP,147 application, or SE98ATP,147 equivalent, this page provides verified JEDEC-grade accuracy specs, HWSON8 package details, EVENT output configuration modes (comparator/interrupt/critical), 11-bit ADC resolution (0.125 °C), and real-world DIMM thermal management design guidance.

Technical Context

The SE98ATP,147 integrates an 11-bit ΔΣ ADC with 8 Hz conversion rate (125 ms period), continuously updating local temperature readings into latched registers. Its SMBus TIMEOUT and ALERT functions are hardware-supported, with programmable hysteresis (0 °C/1.5 °C/3 °C/6 °C) and three independent trip thresholds: Lower Alarm, Upper Alarm, and Critical Trip - all configurable via I²C registers.

It uses a 7-bit slave address (4-bit fixed + 3-bit A0/A1/A2 pins), supports hot-plug operation with 50 ns noise filtering, and initializes to comparator mode with EVENT disabled and hysteresis = 0 °C. The open-drain EVENT output is overvoltage tolerant up to 10 V on A0 and compatible with pull-up voltages from 0.9 V to 3.6 V.

Key Specifications

Pinout & Package

SE98ATP,147 is housed in a 2 mm × 3 mm × 0.8 mm HWSON8 (SOT1069-2) thermally enhanced, leadless package optimized for surface-mount on DDR memory modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar temperature sensor applications.

Compared with SE98ATP,147, SE98APW,118 trades thermal performance for assembly flexibility, while SE97ATP,118 reduces feature set and accuracy to lower BOM cost - neither offers the combination of JEDEC-grade accuracy, 1.7 V compatibility, and SMBus TIMEOUT found in SE98ATP,147.

Availability

SE98ATP,147 is available at Aetrix Electronics and suitable for DDR2/DDR3 memory module manufacturing, enterprise server thermal management, and laptop SO-DIMM production requiring stable component supply and JEDEC-compliant thermal sensing.

Supply support for SE98ATP,147 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and communication infrastructure markets.

The SE98A product line was developed specifically to meet JEDEC JC-42.4 thermal sensor requirements for DDR memory modules, delivering high-accuracy, low-power, and SMBus-integrated temperature monitoring in ultra-compact packages like HWSON8.

FAQ

What is the accuracy specification of the SE98ATP,147 across its full temperature range?

The SE98ATP,147 achieves ±0.5 °C (typical) and ±1 °C (maximum) accuracy between +75 °C and +95 °C per JEDEC JC-42.4 TS3000B1. From +40 °C to +125 °C, accuracy is ±1 °C (typ)/±2 °C (max); from −40 °C to +125 °C, it is ±2 °C (typ)/±3 °C (max). These values are measured under specified test conditions and documented in the official NXP SE98A datasheet Rev. 04.

Does the SE98ATP,147 support SMBus TIMEOUT, and how is it configured?

Yes, the SE98ATP,147 supports SMBus TIMEOUT by default - it resets its internal state machine if SCL is held low for 25–35 ms, preventing bus lockups. TIMEOUT is disabled by writing logic 1 to bit 7 of register 22h (SMBus register). This feature operates across the full 1.7 V to 3.6 V supply range unless shutdown mode is active.

How many SE98ATP,147 devices can share the same I²C bus, and what determines their addresses?

Up to eight SE98ATP,147 devices can coexist on a single I²C bus using the A0, A1, and A2 address pins. Each pin is internally pulled down and sampled at bus access start, forming a 3-bit programmable portion of a 7-bit slave address (fixed 0011xxx pattern). No external pull-ups are needed on A0–A2, and A0 supports 10 V overvoltage tolerance for SPD compatibility.

What are the key differences between the EVENT output's comparator mode and interrupt mode in the SE98ATP,147?

In comparator mode, the SE98ATP,147's EVENT pin behaves like a hardware window comparator - asserting when temperature exits the programmed upper/lower bounds or exceeds critical trip, and remaining asserted until temperature re-enters the window or thresholds are updated. In interrupt mode, EVENT asserts on each boundary crossing and must be cleared via CONFIG register bit 5; it reasserts only on subsequent crossings, enabling precise microprocessor event handling.

Is the SE98ATP,147 compatible with DDR4 memory modules, or is it limited to DDR2/DDR3?

The SE98ATP,147 is explicitly designed and qualified for DDR2 and DDR3 memory modules per JEDEC JC-42.4 Mobile Platform Memory Module Thermal Sensor Component specification. While its electrical interface (I²C/SMBus) and voltage range (1.7–3.6 V) may function in DDR4 systems, it is not validated for DDR4 thermal profiles, timing margins, or JEDEC JC-42.4 revisions applicable to DDR4 - use only in DDR2/DDR3 applications per NXP documentation.