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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5010-B-GM

Name: SI5010-B-GM
Brand: Skyworks Solutions Inc.
SKU: SI5010-B-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5010-B-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 20-VFQFN Exposed Pad

Datasheet:: SI5010-B-GM.pdf

Description:: IC CLOCK/DATA RECOVERY LP 20-QFN

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Product details

Overview

SI5010-B-GM from Silicon Laboratories is a fully-integrated clock and data recovery (CDR) IC for SONET/SDH OC-12/3 and STM-4/1 systems. It recovers timing and data from 155.52 Mbps or 622.08 Mbps serial streams using DSPLL® technology, delivers <1.6 mUI_rms jitter generation, operates from a single 2.5 V supply, and supports industrial temperature range (–40 to 85 °C). It is used in optical transceiver modules and digital cross-connects.

For engineers reviewing the SI5010-B-GM datasheet, SI5010-B-GM pinout, SI5010-B-GM application, or SI5010-B-GM equivalent, this page provides verified technical context, exact pin functions, real-world use cases, and validated alternative options for high-speed telecom CDR design and sourcing.

Technical Context

The SI5010-B-GM implements a digitally controlled phase-locked loop (DSPLL®) that replaces analog loop filters with DSP-based calibration, eliminating external components and reducing board-level noise sensitivity. Its PLL achieves frequency lock by comparing a divided-down VCO output against a 19.44/77.76/155.52 MHz reference clock with ±100 ppm tolerance.

It supports dual-rate operation via RATESEL pin selection (0 = 622.08 Mbps, 1 = 155.52 Mbps), uses CML outputs for DOUT+/DOUT– and CLKOUT+/CLKOUT– with 780–1260 mV_pp swing, and integrates loss-of-lock (LOL) detection with ±600 ppm reacquisition window and PWRDN/CAL-controlled self-calibration.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage	2.5 V ±5% - enables single-rail power architecture and simplifies PCB power delivery for telecom line cards.
Data Rates	155.52 Mbps (OC-3/STM-1) or 622.08 Mbps (OC-12/STM-4) - selectable via RATESEL pin, no external configuration required.
Jitter Generation	1.6 mUI_rms typical - meets Bellcore GR-253-CORE and ITU-T G.958 requirements for SONET/SDH regenerators.
Power Dissipation	293 mW typical at OC-12 - enables thermal management in dense 4×4 mm QFN layouts without forced air cooling.
Input Reference Clock	19.44 / 77.76 / 155.52 MHz ±100 ppm - auto-detected; eliminates need for external rate configuration logic or EEPROM.
Output Interface	CML differential outputs (DOUT+/DOUT–, CLKOUT+/CLKOUT–) - compatible with standard 100 Ω termination and AC-coupled backplane links.
Operating Temperature	–40 to +85 °C - qualified for industrial-grade deployment in carrier-grade add/drop multiplexers and test equipment.

Pinout & Package

SI5010-B-GM is housed in a 4×4 mm, 20-pin QFN package with exposed thermal pad (JEDEC MO-220 VGGD-1 compliant). The GND pad on the bottom must be soldered directly to analog ground plane for optimal jitter performance and thermal dissipation.

Pin/Terminal	Circuit Role	Design Meaning
1	REXT	External bias resistor connection (10 kΩ to GND) - sets internal current sources for low-power, stable CML driver operation.
2,7,11,14	VDD	2.5 V supply input - four dedicated pins reduce IR drop and improve PSRR for high-frequency PLL stability.
3,8,18, GND Pad	GND	Analog/digital ground reference - bottom thermal pad must be connected to solid ground plane to minimize jitter coupling.
4,5	REFCLK+, REFCLK–	Differential reference clock input - accepts 19.44/77.76/155.52 MHz; auto-senses frequency and configures PLL accordingly.
6	LOL	LVTTL loss-of-lock indicator - active-high signal asserts when VCO drift exceeds ±600 ppm relative to REFCLK.
9,10	DIN+, DIN–	Differential serial data input - supports 200–1500 mV_pp swing; accepts both AC- and DC-coupled signals per Table 2.
12,13	DOUT–, DOUT+	CML retimed data output - phase-aligned to CLKOUT rising edge; 780–1260 mV_pp, 100 Ω differential load.
15	PWRDN/CAL	LVTTL dual-function pin - high = powerdown (outputs tied to VDD); falling edge = initiates DSPLL self-calibration.
16,17	CLKOUT–, CLKOUT+	CML recovered clock output - derived from data stream; defaults to REFCLK-derived clock when DIN is inactive.
19	RATESEL	LVTTL data rate select - low = 622.08 Mbps (OC-12), high = 155.52 Mbps (OC-3); weak internal pulldown ensures default OC-3 mode.
20	NC	No connect - must be tied to GND per datasheet to prevent floating node noise coupling into analog core.

Key Features

Feature	Design Value
DSPLL® architecture	Replaces analog loop filter with digital signal processing - eliminates 3–5 external passive components and associated board noise sensitivity.
Auto-reference clock detection	Identifies 19.44/77.76/155.52 MHz REFCLK without configuration - removes need for strap resistors or firmware initialization.
Integrated LOL monitoring	Hardware lock-detect circuit compares divided VCO vs. REFCLK frequency - provides deterministic alarm for system fault reporting.
Single-supply 2.5 V operation	Eliminates need for 3.3 V or 1.8 V auxiliary rails - reduces BOM count and simplifies power sequencing in multi-channel CDR designs.
4×4 mm QFN footprint	Enables high-density placement in space-constrained optical modules - matches industry-standard form factor for pluggable transceivers.

Applications

Optical Transceiver Modules	Digital Cross-Connect Systems
Use Scenario: Embedded in SFP/SFP+ modules to recover clock and data from incoming fiber optic signals before retiming and forwarding to host ASIC. IC Role / Device Role / Timing Role: Primary CDR element performing clock extraction, data retiming, and jitter cleanup at line rate. Use Value: Enables compliance with SONET/SDH jitter transfer and generation masks (GR-253-CORE) without external filtering or tuning.	Use Scenario: Installed on central office switching cards to regenerate clean clock/data for inter-shelf serial links operating at OC-12/STM-4 rates. IC Role / Device Role / Timing Role: Line-interface CDR providing low-jitter clock distribution and signal integrity restoration across backplane traces. Use Value: Delivers 1.6 mUI_rms jitter generation and >20 dB input return loss - maintains BER <10⁻¹² over 20-year service life.
Add/Drop Multiplexers	SONET/SDH Test Equipment
Use Scenario: Used in channelized ADM line cards to extract and retime individual OC-3 or OC-12 tributaries from aggregate OC-48 signals. IC Role / Device Role / Timing Role: Rate-flexible CDR supporting both 155.52 Mbps and 622.08 Mbps via RATESEL pin - no hardware change needed. Use Value: Dual-rate capability reduces inventory SKUs and enables field-upgradable bandwidth without PCB redesign.	Use Scenario: Integrated into bit-error-rate testers (BERTs) and jitter analyzers to validate compliance of DUTs against GR-253-CORE mask requirements. IC Role / Device Role / Timing Role: Reference CDR generating known-clean recovered clock/data for stimulus and measurement synchronization. Use Value: Sub-2 mUI_rms jitter floor provides metrology-grade timing reference - critical for accurate jitter tolerance and transfer testing.

Optical Transceiver Modules

Digital Cross-Connect Systems

Use Scenario: Embedded in SFP/SFP+ modules to recover clock and data from incoming fiber optic signals before retiming and forwarding to host ASIC.

IC Role / Device Role / Timing Role: Primary CDR element performing clock extraction, data retiming, and jitter cleanup at line rate.

Use Value: Enables compliance with SONET/SDH jitter transfer and generation masks (GR-253-CORE) without external filtering or tuning.

Use Scenario: Installed on central office switching cards to regenerate clean clock/data for inter-shelf serial links operating at OC-12/STM-4 rates.

IC Role / Device Role / Timing Role: Line-interface CDR providing low-jitter clock distribution and signal integrity restoration across backplane traces.

Use Value: Delivers 1.6 mUI_rms jitter generation and >20 dB input return loss - maintains BER <10⁻¹² over 20-year service life.

Add/Drop Multiplexers

SONET/SDH Test Equipment

Use Scenario: Used in channelized ADM line cards to extract and retime individual OC-3 or OC-12 tributaries from aggregate OC-48 signals.

IC Role / Device Role / Timing Role: Rate-flexible CDR supporting both 155.52 Mbps and 622.08 Mbps via RATESEL pin - no hardware change needed.

Use Value: Dual-rate capability reduces inventory SKUs and enables field-upgradable bandwidth without PCB redesign.

Use Scenario: Integrated into bit-error-rate testers (BERTs) and jitter analyzers to validate compliance of DUTs against GR-253-CORE mask requirements.

IC Role / Device Role / Timing Role: Reference CDR generating known-clean recovered clock/data for stimulus and measurement synchronization.

Use Value: Sub-2 mUI_rms jitter floor provides metrology-grade timing reference - critical for accurate jitter tolerance and transfer testing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock and data recovery applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX3675	Operates at 3.3 V supply; higher 450 mW power; requires external loop filter components; supports only OC-12 rate.	Limited to single-rate OC-12 systems; less suitable for space-constrained or low-power modules due to larger TQFP package and higher thermal load.	Choose MAX3675 only if existing 3.3 V infrastructure prohibits voltage rail change and OC-12-only operation is sufficient.
ICS8430-01	Requires external VCXO and loop filter; 3.3 V supply; jitter generation 2.5 mUI_rms; no integrated LOL indicator.	Needs additional timing components and layout area; lacks built-in lock monitoring - increases system-level validation effort for telecom deployments.	Select ICS8430-01 only when legacy design reuse mandates discrete PLL architecture and higher jitter budget is acceptable.

Compared with MAX3675 and ICS8430-01, SI5010-B-GM offers lower power (293 mW), smaller footprint (4×4 mm QFN), integrated DSPLL® eliminating external filters, and guaranteed sub-2 mUI_rms jitter - making it optimal for next-generation compact, low-power SONET/SDH line interfaces.

Availability

SI5010-B-GM is available at Aetrix Electronics and suitable for optical transceiver modules, digital cross-connect systems, and SONET/SDH test equipment requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for SI5010-B-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in precision timing, MCU, and connectivity solutions for communications, industrial, and consumer markets.

The SI5010-B-GM belongs to Silicon Labs' high-speed timing product line, designed specifically for SONET/SDH clock and data recovery in carrier-grade optical infrastructure where jitter performance, power efficiency, and integration density are critical.

FAQ

What data rates does the SI5010-B-GM support?

The SI5010-B-GM supports two fixed data rates: 155.52 Mbps (OC-3/STM-1) and 622.08 Mbps (OC-12/STM-4). Rate selection is controlled by the RATESEL pin (low = OC-12, high = OC-3), and the device auto-detects the correct reference clock frequency (19.44/77.76/155.52 MHz) without external configuration. This dual-rate capability is built into the SI5010-B-GM silicon and verified across –40 to +85 °C.

Does the SI5010-B-GM require external loop filter components?

No, the SI5010-B-GM does not require external loop filter components. It uses Silicon Labs' DSPLL® technology, which replaces the analog loop filter with an on-chip digital signal processing algorithm. This eliminates sensitive noise entry points and is confirmed in the functional block diagram and Section 4.1 of the datasheet. The SI5010-B-GM only requires a single 10 kΩ resistor on REXT for bias current setting.

How is loss-of-lock indicated on the SI5010-B-GM?

The SI5010-B-GM provides a dedicated LVTTL output pin (LOL) that asserts high when the recovered clock frequency deviates from the reference clock by more than ±600 ppm. This behavior is specified in Table 4 (LOL threshold) and described in Section 4.5. The LOL signal remains asserted during reacquisition and is disabled during PWRDN/CAL high state - all documented for the SI5010-B-GM in Rev. 1.4.

What is the recommended termination for SI5010-B-GM differential inputs and outputs?

For differential inputs (DIN+, DIN–, REFCLK+, REFCLK–), the datasheet recommends AC coupling with 0.1 µF capacitors and 50 Ω series termination to match 50 Ω source impedance. For differential outputs (DOUT+, DOUT–, CLKOUT+, CLKOUT–), CML drivers require 100 Ω differential load (50 Ω to VDD per leg) with optional 0.1 µF AC coupling - as shown in Figures 6 and 9. These values are validated for the SI5010-B-GM and ensure signal integrity at OC-12/STM-4 rates.

Is the SI5010-B-GM RoHS-compliant and lead-free?

Yes, the SI5010-B-GM is RoHS6-compliant and lead-free. Per the Ordering Guide (page 16), it features a NiPdAu pre-plated finish fully compatible with both leaded and lead-free assembly processes. The "-GM" suffix explicitly denotes green (Pb-free) packaging, and the device meets JEDEC/IPC J-STD-020C reflow specifications - confirmed for SI5010-B-GM in Rev. 1.4.

SI5010-B-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL®

Package/Case:: 20-VFQFN Exposed Pad

Packaging:: Tube

Product Status:: Obsolete

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: SONET/SDH, ATM applications

Input:: Clock

Output:: CML

Number of Circuits:: 1

Ratio - Input:Output:: 1:2

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 666MHz

Voltage - Supply:: 2.375V ~ 2.625V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 20-QFN (4x4)

SI5010-B-GM FAQ

1.How can I place an order for SI5010-B-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5010-B-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5010-B-GM reliable?

The price and inventory of SI5010-B-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5010-B-GM is usually 5 days.

3.What payment methods are accepted for SI5010-B-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5010-B-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5010-B-GM?

SI5010-B-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5010-B-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5010-B-GM?

For technical support, including SI5010-B-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5010-B-GM requirements.

6.How does Aetrix verify that SI5010-B-GM is sourced from the original manufacturer or authorized distributors?

All SI5010-B-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5010-B-GM meets industry standards.

7.What is the process for return or replacement of SI5010-B-GM?

All SI5010-B-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5010-B-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5010-B-GM part is unused and in its original packaging.

Return procedure for SI5010-B-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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