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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5018-B-GMR

Name: SI5018-B-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5018-B-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5018-B-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 20-VFQFN Exposed Pad

Datasheet:: SI5018-B-GMR.pdf

Description:: IC CLOCK/DATA RECOVERY 20-QFN

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Product details

Overview

SI5018-B-GMR from Silicon Laboratories is a fully-integrated clock and data recovery (CDR) IC for OC-48/STM-16 (2.488–2.7 Gbps) serial links with forward error correction (FEC) support. It performs jitter-tolerant clock extraction, data retiming, and low-jitter CML clock/data output using DSPLL™ technology. It operates from a single 2.5 V supply across –40 to 85 °C and delivers 2.9 mUIrms jitter generation in SONET/SDH-compliant systems.

For engineers reviewing the SI5018-B-GMR datasheet, SI5018-B-GMR pinout, SI5018-B-GMR application, or SI5018-B-GMR equivalent, this page provides verified technical context, validated pin functions, confirmed SONET/SDH jitter compliance, real-world FEC timing behavior at 2.7 Gbps, and direct alternative options for optical transport layer CDR replacement.

Technical Context

The SI5018-B-GMR implements a digital signal processing–based DSPLL™ architecture that replaces analog loop filters, eliminating external components and reducing board-level noise coupling. Its PLL locks to differential input data at OC-48/STM-16 rates (2.488 GHz nominal) or FEC-enhanced 2.666 GHz streams, while simultaneously synchronizing to one of three reference clock frequencies (19.44/77.76/155.52 MHz) via automatic ratio detection.

It integrates dual CML output drivers for retimed DOUT+/- and CLKOUT+/- with 780–1260 mVpp swing into 100 Ω loads, plus LVTTL-compatible control pins (PWRDN/CAL, LOL) referenced to 2.5 V supply. Bias current is set by an external 10 kΩ resistor on REXT, enabling precise power optimization.

Key Specifications

Parameter	Value and Actual Design Meaning
Data Rate Support	OC-48/STM-16 (2.488 GHz) and FEC-enhanced 2.666–2.7 Gbps - enables deployment in SONET regenerators and FEC-capable optical transceivers.
Jitter Generation	2.9 mUIrms typical - meets GR-253-CORE and G.958 requirements for recovered clock/data integrity in telecom infrastructure.
Supply Voltage	2.5 V ±5% - single-rail operation simplifies power delivery and eliminates level-shifting for adjacent 2.5 V logic.
Power Dissipation	270 mW typical at OC-48 - enables high-density placement in space-constrained add/drop multiplexers and line cards.
Operating Temperature	–40 to 85 °C industrial range - supports deployment in uncontrolled telecom cabinets and outdoor optical nodes.
Input Sensitivity	200–1500 mVpp differential (DIN/REFCLK) - accommodates both AC-coupled and DC-coupled interface designs without external amplification.
Output Interface	CML outputs (DOUT/CLKOUT) with 100 Ω load termination - ensures impedance-matched routing to FPGA SerDes or laser driver inputs.

Pinout & Package

SI5018-B-GMR is housed in a 4×4 mm, 20-pin QFN package with exposed thermal pad (JEDEC MO-220 VGGD-1). The GND pad on the bottom must be soldered directly to the PCB ground plane for thermal and electrical performance.

Pin/Terminal	Circuit Role	Design Meaning
1	REXT	External bias resistor connection - sets internal current sources via 10 kΩ (1%) resistor to GND for stable low-power operation.
4–5	REFCLK+/REFCLK–	Differential reference clock input - auto-detects 19.44/77.76/155.52 MHz to center VCO at OC-48/FEC rates without configuration.
6	LOL	LVTTL loss-of-lock indicator - asserts high when recovered clock deviates >450–750 ppm from REFCLK, signaling PLL unlock.
9–10	DIN+/DIN–	Differential high-speed data input - accepts 200–1500 mVpp OC-48 or FEC data; supports AC/DC coupling per layout guidelines.
12–13	DOUT–/DOUT+	CML retimed data output - phase-aligned to CLKOUT rising edge; 780–1260 mVpp into 100 Ω, ac-coupled to downstream receivers.
15	PWRDN/CAL	Multi-function LVTTL input - high = output shutdown (power save); falling edge = initiates DSPLL self-calibration after power-up.
16–17	CLKOUT–/CLKOUT+	CML recovered clock output - derived from data stream or REFCLK during idle; 550–1260 mVpp into 100 Ω load.
2,7,11,14	VDD	2.5 V supply pins - four dedicated VDD connections minimize IR drop and improve PSRR for jitter-sensitive analog blocks.
3,8,18,19,20 + Pad	GND	Ground terminals - six perimeter pins plus center thermal pad ensure low-inductance return path for CML drivers and DSPLL core.

Key Features

Feature	Design Value
DSPLL™ digital loop filter	Eliminates external RC components - reduces BOM count, PCB area, and sensitivity to board noise, ensuring consistent GR-253 jitter compliance.
FEC-aware reference clock detection	Auto-selects 1/16, 1/32, or 1/128 VCO division ratio - enables seamless transition between standard OC-48 and 2.7 Gbps FEC modes without firmware or pin strapping.
Integrated bias generation	10 kΩ REXT sets precision bias currents - achieves 270 mW typical power at 2.5 V while maintaining jitter performance across temperature.
Loss-of-lock monitoring	Dedicated LOL pin with ppm-based lock window (±450–750 ppm) - provides deterministic status for system fault reporting and channel failover logic.
Powerdown + calibration dual-mode pin	PWRDN/CAL combines output disable and DSPLL recalibration - allows runtime power gating and post-power-up jitter optimization in hot-swap line cards.

Applications

SONET/SDH Regenerator	Optical Transceiver Module
Use Scenario: Reconditioning degraded OC-48 signals in long-haul fiber spans where jitter accumulation exceeds ITU-T G.823 limits. IC Role / Device Role / Timing Role: Clock and data recovery IC extracting clean timing from noisy serial input and retiming data onto low-jitter CML outputs. Use Value: 2.9 mUIrms jitter generation and >40 UIPP jitter tolerance meet GR-253-CORE mask requirements, enabling multi-span repeater deployment.	Use Scenario: Embedded CDR in SFP/SFP+ modules supporting FEC-enabled 2.7 Gbps data rates for extended reach DWDM links. IC Role / Device Role / Timing Role: High-speed CDR providing synchronized CLKOUT/DOUT to laser driver and host-side SerDes. Use Value: Automatic REFCLK ratio detection (19.44/84.375/168.75 MHz) eliminates manual configuration for FEC vs. non-FEC variants.
Add/Drop Multiplexer	SONET Test Equipment
Use Scenario: Channel extraction and reinsertion in metro ADMs requiring low-latency, deterministic retiming across multiple OC-48 tributaries. IC Role / Device Role / Timing Role: Retimer IC delivering phase-aligned DOUT and CLKOUT with <270 ps clock-to-data delay stability. Use Value: 225–270 ps t_C-D consistency across temperature ensures predictable timing budget allocation in multi-channel backplanes.	Use Scenario: Jitter stress testing and BER validation of SONET equipment using calibrated CDR as reference receiver. IC Role / Device Role / Timing Role: Reference-grade CDR generating compliant recovered clock for jitter transfer/tolerance measurement setups. Use Value: Exceeds Bellcore GR-253 jitter specifications - validates DUT performance against industry-standard masks.

SONET/SDH Regenerator

Optical Transceiver Module

Use Scenario: Reconditioning degraded OC-48 signals in long-haul fiber spans where jitter accumulation exceeds ITU-T G.823 limits.

IC Role / Device Role / Timing Role: Clock and data recovery IC extracting clean timing from noisy serial input and retiming data onto low-jitter CML outputs.

Use Value: 2.9 mUIrms jitter generation and >40 UIPP jitter tolerance meet GR-253-CORE mask requirements, enabling multi-span repeater deployment.

Use Scenario: Embedded CDR in SFP/SFP+ modules supporting FEC-enabled 2.7 Gbps data rates for extended reach DWDM links.

IC Role / Device Role / Timing Role: High-speed CDR providing synchronized CLKOUT/DOUT to laser driver and host-side SerDes.

Use Value: Automatic REFCLK ratio detection (19.44/84.375/168.75 MHz) eliminates manual configuration for FEC vs. non-FEC variants.

Add/Drop Multiplexer

SONET Test Equipment

Use Scenario: Channel extraction and reinsertion in metro ADMs requiring low-latency, deterministic retiming across multiple OC-48 tributaries.

IC Role / Device Role / Timing Role: Retimer IC delivering phase-aligned DOUT and CLKOUT with <270 ps clock-to-data delay stability.

Use Value: 225–270 ps t_C-D consistency across temperature ensures predictable timing budget allocation in multi-channel backplanes.

Use Scenario: Jitter stress testing and BER validation of SONET equipment using calibrated CDR as reference receiver.

IC Role / Device Role / Timing Role: Reference-grade CDR generating compliant recovered clock for jitter transfer/tolerance measurement setups.

Use Value: Exceeds Bellcore GR-253 jitter specifications - validates DUT performance against industry-standard masks.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock and data recovery applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MAX3875E	Higher 350 mW power, requires external loop filter, 3.3 V supply only - lacks DSPLL integration and FEC auto-detection.	Used in legacy OC-48 test gear; not optimized for FEC or compact 4×4 mm layouts.	Choose MAX3875E only if existing 3.3 V infrastructure prohibits voltage conversion and DSPLL benefits are secondary.
ICS87201AGI	Supports OC-48 but no FEC mode; 3.3 V tolerant I/O, 4.5×4.5 mm TQFP package - larger footprint and higher 400 mW dissipation.	Deployed in older add/drop multiplexers with through-hole or larger surface-mount constraints.	Select ICS87201AGI when board space permits larger package and FEC capability is unnecessary.

Compared with SI5018-B-GMR, MAX3875E demands external filtering and higher supply voltage, increasing design complexity and power; ICS87201AGI occupies 26% more PCB area and lacks FEC support, limiting use in next-gen optical modules requiring 2.7 Gbps operation.

Availability

SI5018-B-GMR is available at Aetrix Electronics and suitable for SONET/SDH regenerators, optical transceiver modules, and add/drop multiplexers requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for SI5018-B-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in timing, wireless, and sensor technologies for communications, industrial, and consumer markets.

The Si5018-B-GMR belongs to Silicon Labs' SiPHY™ family of high-speed communication ICs, engineered specifically for low-jitter, low-power clock and data recovery in SONET/SDH optical transport systems.

FAQ

What data rates does the SI5018-B-GMR support?

The SI5018-B-GMR supports OC-48/STM-16 at 2.488 GHz and FEC-enhanced streams up to 2.7 Gbps. It automatically detects reference clock frequencies of 19.44 MHz, 77.76 MHz, or 155.52 MHz to configure the correct VCO division ratio. This enables seamless interoperability between standard and FEC-enabled optical links without hardware or software reconfiguration. SI5018-B-GMR maintains full jitter compliance across all supported rates.

How does the DSPLL™ architecture in SI5018-B-GMR improve jitter performance?

The DSPLL™ in SI5018-B-GMR replaces analog loop filter components with digital signal processing, eliminating sensitive noise entry points from external resistors and capacitors. This architecture reduces susceptibility to board-level interference and ensures consistent jitter generation of ≤2.9 mUIrms - meeting GR-253-CORE and G.958 requirements. SI5018-B-GMR achieves this without sacrificing lock time or acquisition stability, even under transient thermal conditions.

What is the function of the PWRDN/CAL pin on SI5018-B-GMR?

The PWRDN/CAL pin on SI5018-B-GMR serves two distinct functions: driving it high disables DOUT and CLKOUT drivers to reduce power consumption, while a high-to-low transition initiates DSPLL self-calibration. Calibration requires a valid REFCLK and occurs within 1.5 ms. SI5018-B-GMR uses this pin to enable both runtime power gating and post-power-up jitter optimization - critical for hot-swap line cards and energy-conscious optical modules.

Does SI5018-B-GMR require external passive components for basic operation?

SI5018-B-GMR requires only one external component for normal operation: a 10 kΩ (1%) resistor between REXT and GND to set internal bias currents. Unlike traditional CDRs, it eliminates external loop filter components thanks to DSPLL™. AC-coupling capacitors (0.1 µF) and termination resistors (100 Ω) are recommended for signal integrity but not strictly required for DC-coupled interfaces. SI5018-B-GMR's minimal BOM reduces cost and layout complexity.

What is the significance of the LOL pin on SI5018-B-GMR?

The LOL (Loss-of-Lock) pin on SI5018-B-GMR is an LVTTL output that asserts high when the recovered clock frequency deviates from the reference clock by more than 450–750 ppm, indicating PLL unlock. It provides deterministic status for system-level fault handling, such as triggering channel failover or initiating reacquisition sequences. SI5018-B-GMR holds LOL inactive during PWRDN/CAL assertion, preventing false alarms during controlled power-down events.

SI5018-B-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: SiPHY™, DSPLL®

Package/Case:: 20-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: SONET/SDH, ATM applications

Input:: Clock

Output:: CML

Number of Circuits:: 1

Ratio - Input:Output:: 1:2

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 2.7GHz

Voltage - Supply:: 2.375V ~ 2.625V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 20-QFN (4x4)

SI5018-B-GMR FAQ

1.How can I place an order for SI5018-B-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5018-B-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5018-B-GMR reliable?

The price and inventory of SI5018-B-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5018-B-GMR is usually 5 days.

3.What payment methods are accepted for SI5018-B-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5018-B-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5018-B-GMR?

SI5018-B-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5018-B-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5018-B-GMR?

For technical support, including SI5018-B-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5018-B-GMR requirements.

6.How does Aetrix verify that SI5018-B-GMR is sourced from the original manufacturer or authorized distributors?

All SI5018-B-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5018-B-GMR meets industry standards.

7.What is the process for return or replacement of SI5018-B-GMR?

All SI5018-B-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5018-B-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5018-B-GMR part is unused and in its original packaging.

Return procedure for SI5018-B-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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