Skyworks Solutions Inc. SI5018-BM

Overview

SI5018-BM from Silicon Laboratories is a fully-integrated clock and data recovery (CDR) IC for OC-48/STM-16 (2.488 GHz) and FEC-enhanced 2.7 Gbps serial links. It performs timing extraction and data retiming using DSPLL™ technology, delivers 2.9 mUIrms jitter generation, operates from a single 2.5 V supply, and supports industrial temperature range (–40 to 85 °C). It is deployed in optical transceiver modules and SONET/SDH regenerators.

For engineers reviewing the SI5018-BM datasheet, SI5018-BM pinout, SI5018-BM application, or SI5018-BM equivalent, key selection criteria include jitter compliance with Bellcore GR-253-CORE, DSPLL™ self-calibration behavior, CML output drive capability, REXT bias resistor requirement, and loss-of-lock (LOL) alarm functionality under reference clock absence.

Technical Context

The SI5018-BM implements a digital signal processing (DSP)-based DSPLL™ architecture that replaces analog loop filter components, eliminating board-level noise coupling paths and enabling guaranteed SONET/SDH jitter compliance. Its PLL uses a divided-down VCO output compared to REFCLK to detect lock status, with LOL assertion triggered at ±600 ppm frequency deviation.

It supports dual-mode operation: standard OC-48/STM-16 (2.488 GHz) and FEC-enabled 2.7 Gbps mode, where reference clock selection (19.44 MHz, 83.31 MHz, or 166.63 MHz) determines VCO centering via 128×, 32×, or 16× multiplication. Input termination accommodates both differential and single-ended DIN/REFCLK drive, with 100 Ω differential input impedance and 200–1500 mVPP differential swing support.

Key Specifications

Pinout & Package

The SI5018-BM is housed in a 4×4 mm, 20-pin micro leadframe package (MLP) with exposed thermal pad. The package features 16 signal terminals and 4 dedicated VDD/GND pins plus bottom-side GND pad for low-inductance grounding.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock and data recovery applications.

Compared with MAX3875E and ICS872002, the SI5018-BM provides superior jitter performance, eliminates external loop filter design complexity, supports FEC-enhanced 2.7 Gbps operation, and enables automatic reference clock configuration-making it optimal for next-generation optical infrastructure requiring guaranteed compliance and layout flexibility.

Availability

SI5018-BM is available at Aetrix Electronics and suitable for optical transceiver modules, SONET/SDH regenerators, and add/drop multiplexers requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for SI5018-BM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in precision timing, wireless, and mixed-signal ICs for communications, computing, and industrial markets.

The SI5018-BM belongs to Silicon Labs' SiPHY™ family of high-speed CDRs, engineered specifically for SONET/SDH optical infrastructure where low jitter, small footprint, and single-supply operation are critical design constraints.

FAQ

What is the primary function of the SI5018-BM in a SONET/SDH system?

The SI5018-BM serves as a clock and data recovery IC that extracts precise timing information and retimes serial data from OC-48/STM-16 (2.488 GHz) or FEC-enhanced 2.7 Gbps inputs. In a SONET/SDH system, it ensures jitter-clean clock and data outputs compliant with Bellcore GR-253-CORE, enabling reliable signal regeneration and synchronization. The SI5018-BM achieves this using DSPLL™ technology and integrated CML drivers.

How does the SI5018-BM handle reference clock detection and configuration?

The SI5018-BM automatically detects whether the applied REFCLK is 19.44 MHz, 83.31 MHz, or 166.63 MHz and configures its internal VCO multiplication ratio accordingly (128×, 32×, or 16×). This eliminates manual configuration or external strapping. The SI5018-BM uses continuous monitoring of REFCLK frequency to center the VCO output between 2.488 GHz and 2.7 GHz, ensuring correct operation across all supported modes.

What is the role of the REXT pin on the SI5018-BM, and what value resistor is required?

The REXT pin on the SI5018-BM connects to an external 10 kΩ (1%) resistor tied to GND, which sets internal bias currents for optimal power efficiency and process/voltage/temperature stability. This external biasing reduces power versus on-die resistors and improves repeatability. Omitting or misvaluing the REXT resistor causes incorrect biasing, increased power consumption, and potential jitter degradation in the SI5018-BM.

Does the SI5018-BM support both differential and single-ended input drive for DIN and REFCLK?

Yes, the SI5018-BM supports both differential and single-ended drive for DIN+/- and REFCLK+/- inputs. When driven single-endedly, the active input must exceed 200 mVPP differential swing, and the unused input must be AC-coupled to ground. For differential drive, the voltage difference between pins must exceed 200 mVPP. Both configurations maintain full 100 Ω input impedance and jitter performance in the SI5018-BM.

What happens to the LOL (Loss-of-Lock) output when the REFCLK signal is removed?

When REFCLK is removed, the LOL output of the SI5018-BM is asserted high to indicate unknown lock status, as the PLL cannot compare recovered clock frequency to a reference. This differs from normal out-of-lock conditions (triggered by >±600 ppm deviation), where LOL toggles during reacquisition attempts. The SI5018-BM does not assert LOL during PWRDN/CAL activation, preserving diagnostic clarity.