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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI52111-B6-GM2

Name: SI52111-B6-GM2
Brand: Skyworks Solutions Inc.
SKU: SI52111-B6-GM2
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI52111-B6-GM2

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 10-WFDFN Exposed Pad

Datasheet:: SI52111-B6-GM2.pdf

Description:: IC OSC PCI EXPRESS 1OUTPUT

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI52111-B6-GM2 from Skyworks Solutions is a PCIe Gen 3/Gen 4 single-output clock generator with HCSL differential output, 100 MHz frequency, –0.5% down spread spectrum modulation, and 10-pin TDFN (3×3 mm) package. It accepts a 25 MHz crystal or clock input, operates from 3.3 V, and targets PCIe-compliant host systems requiring low-jitter timing in space-constrained embedded designs.

For engineers reviewing the SI52111-B6-GM2 datasheet, SI52111-B6-GM2 pinout, SI52111-B6-GM2 application, or SI52111-B6-GM2 equivalent, key selection criteria include PCIe Gen 3 SRNS and Gen 4 common clock compliance, 0.5% spread spectrum capability, 30–33 kHz modulation frequency, sub-1 ps RMS phase jitter (Gen 3), and compatibility with 25 MHz parallel-resonant crystals with 12–15 pF load capacitance.

Technical Context

The SI52111-B6-GM2 integrates a PLL-based clock synthesis architecture optimized for PCIe Gen 1–4 common clock and Gen 3 SRNS modes. Its internal PLL bandwidth is configurable between 2–4 MHz or 2–5 MHz, supporting CDR at 10 MHz to meet stringent phase jitter requirements across multiple PCIe generations.

It features a low-power HCSL output buffer delivering 100 MHz differential clocks at 0.7 V swing without external termination resistors. The device supports both crystal (XIN/XOUT) and single-ended clock (CLKIN) reference inputs, with dedicated power (VDD), ground (VSS), and no-connect (NC) terminals mapped to its 10-pin TDFN footprint.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequency	100 MHz - precisely matches PCIe reference clock requirement for root complex and endpoint timing.
PCIe Compliance	Gen 1/2/3/4 common clock + Gen 3 SRNS - validated against PCI-SIG specifications for interoperability in multi-lane systems.
Phase Jitter (Gen 3)	0.4–1.0 ps RMS (10 kHz–Nyquist) - meets PCIe Gen 3 SRNS specification for low-noise data recovery.
Spread Spectrum	–0.5% down spread, 30–33 kHz modulation - reduces EMI peak emissions without violating PCIe clock tolerance limits.
Supply Voltage	3.3 V ± 10% - compatible with standard I/O rail; no sequencing required during power-up.
Operating Temperature	–40 °C to +85 °C - qualified for extended industrial and consumer embedded environments.
Power Consumption	13 mA typical - enables thermal efficiency in dense PCB layouts with minimal heat dissipation.

Pinout & Package

SI52111-B6-GM2 uses a 10-pin TDFN package (3.0 × 3.0 mm, 0.75 mm height) with exposed thermal pad. Pin 1 is top-left corner (marking dot adjacent), pins numbered counter-clockwise. Two VDD pins (1, 10) and two VSS pins (4, 5) provide low-impedance power/ground distribution; XIN/CLKIN (pin 3) and XOUT (pin 2) support crystal or clock reference; DIFF1 outputs (pins 6, 7) deliver complementary HCSL signals; pins 8 and 9 are NC.

Pin/Terminal	Circuit Role	Design Meaning
1, 10 VDD	Power supply input	Dual 3.3 V supply connections reduce IR drop and improve PSRR for stable PLL operation.
4, 5 VSS	Ground reference	Dual ground pins minimize return path inductance and suppress ground bounce on high-speed outputs.
3 XIN/CLKIN	Reference input	Accepts either 25 MHz crystal (parallel resonance) or 25 MHz single-ended clock; VIH/VIL thresholds ensure robust logic-level recognition.
2 XOUT	Crystal oscillator output	Drives crystal in Pierce configuration; must be floated when using external CLKIN only.
6, 7 DIFF1	Differential clock output	Complementary 100 MHz HCSL outputs (0.7 V swing, 300–550 mV crossing point) drive PCIe lanes directly without termination.
8, 9 NC	No connect	Must remain unconnected per design; floating these pins avoids unintended coupling or parasitic oscillation.

Key Features

Feature	Design Value
PCIe Gen 4 common clock compliance	Validated RMS phase jitter ≤1.0 ps (10 kHz–Nyquist) ensures reliable link training and stability in Gen 4 x16 configurations.
Integrated spread spectrum (–0.5%)	Reduces EMI by spreading energy across 30–33 kHz band-eliminates need for external modulation circuitry or layout changes.
HCSL output without termination	On-die 50 Ω source impedance enables direct connection to PCIe receivers, saving board space and BOM cost vs. external resistors.
Low-power active mode (13 mA)	Enables use in thermally constrained applications such as NAS enclosures and compact wireless gateways without forced cooling.
Extended temperature range (–40 to +85 °C)	Supports deployment in uncontrolled ambient environments including industrial edge nodes and outdoor networking equipment.

Applications

Network Attached Storage	Wireless Access Point
Use Scenario: Timing synchronization for dual-controller PCIe SSD arrays and SATA backplanes in compact NAS chassis. IC Role / Device Role / Timing Role: Primary PCIe reference clock generator providing 100 MHz common clock to root complex and storage controllers. Use Value: Sub-1 ps Gen 3 SRNS jitter ensures error-free 8 GT/s link negotiation; spread spectrum lowers conducted EMI to meet FCC Class B limits in metal enclosures.	Use Scenario: Clocking baseband processors and PCIe-connected Wi-Fi 6/6E radios in enterprise-grade APs with multi-band concurrency. IC Role / Device Role / Timing Role: Single-output PCIe Gen 4 clock source for SoC host interface and RF front-end synchronization. Use Value: 3.3 V operation and 13 mA draw enable integration into power-sensitive 12 V PoE-powered designs; 3×3 mm TDFN saves critical PCB area near RF sections.
Routers	Multi-function Printer
Use Scenario: High-density core routing platforms with multiple PCIe-based NICs, switch fabrics, and crypto accelerators. IC Role / Device Role / Timing Role: Centralized clock generator distributing synchronized 100 MHz reference to all PCIe endpoints via common clock topology. Use Value: Dual VDD/VSS pins and low cycle-to-cycle jitter (≤70 ps) maintain signal integrity across long trace runs and multi-layer stackups.	Use Scenario: Embedded controller timing in multifunction printers with PCIe-scanned image pipelines and USB 3.x host interfaces. IC Role / Device Role / Timing Role: PCIe Gen 3 clock source for document processing ASICs and peripheral bridge ICs. Use Value: –40 to +85 °C rating accommodates thermal cycling in office environments; no-termination HCSL simplifies routing to mixed-signal subsystems.

Network Attached Storage

Wireless Access Point

Use Scenario: Timing synchronization for dual-controller PCIe SSD arrays and SATA backplanes in compact NAS chassis.

IC Role / Device Role / Timing Role: Primary PCIe reference clock generator providing 100 MHz common clock to root complex and storage controllers.

Use Value: Sub-1 ps Gen 3 SRNS jitter ensures error-free 8 GT/s link negotiation; spread spectrum lowers conducted EMI to meet FCC Class B limits in metal enclosures.

Use Scenario: Clocking baseband processors and PCIe-connected Wi-Fi 6/6E radios in enterprise-grade APs with multi-band concurrency.

IC Role / Device Role / Timing Role: Single-output PCIe Gen 4 clock source for SoC host interface and RF front-end synchronization.

Use Value: 3.3 V operation and 13 mA draw enable integration into power-sensitive 12 V PoE-powered designs; 3×3 mm TDFN saves critical PCB area near RF sections.

Routers

Multi-function Printer

Use Scenario: High-density core routing platforms with multiple PCIe-based NICs, switch fabrics, and crypto accelerators.

IC Role / Device Role / Timing Role: Centralized clock generator distributing synchronized 100 MHz reference to all PCIe endpoints via common clock topology.

Use Value: Dual VDD/VSS pins and low cycle-to-cycle jitter (≤70 ps) maintain signal integrity across long trace runs and multi-layer stackups.

Use Scenario: Embedded controller timing in multifunction printers with PCIe-scanned image pipelines and USB 3.x host interfaces.

IC Role / Device Role / Timing Role: PCIe Gen 3 clock source for document processing ASICs and peripheral bridge ICs.

Use Value: –40 to +85 °C rating accommodates thermal cycling in office environments; no-termination HCSL simplifies routing to mixed-signal subsystems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si52111-B5-GM2	No spread spectrum; identical pinout, package, and electrical specs except SRNG = 0%	Suitable where EMI reduction is handled externally or not required (e.g., shielded modules)	Select B5 if system-level EMI mitigation is implemented elsewhere; B6 preferred for standalone compliance.
ICS843002AGI-01LFT	LVDS output (not HCSL); 100 MHz fixed; no spread spectrum; 8-pin SOIC package	Requires external 50 Ω termination; larger footprint; limited to commercial temp (0 to +70 °C)	Use only if LVDS interface is mandatory and board layout allows SOIC placement; not drop-in compatible.

Compared with SI52111-B5-GM2, the SI52111-B6-GM2 adds verified –0.5% spread spectrum for EMI control without altering PCB layout or power delivery. Against ICS843002AGI-01LFT, it offers HCSL drive, smaller TDFN packaging, extended temperature range, and integrated spread spectrum-enabling direct PCIe Gen 4 compliance in space- and thermal-constrained designs.

Availability

SI52111-B6-GM2 is available at Aetrix Electronics and suitable for network attached storage, wireless access points, and routers requiring stable component supply, consistent lead times, and full lifecycle support through obsolescence management.

Supply support for SI52111-B6-GM2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si52111 family delivers PCIe-optimized clock generation for high-speed serial interconnects, designed specifically to meet the jitter, spread spectrum, and packaging demands of next-generation embedded computing and networking platforms.

FAQ

What is the primary function of the SI52111-B6-GM2 in a PCIe system?

The SI52111-B6-GM2 serves as a single-output PCIe Gen 3/Gen 4 common clock generator, producing a 100 MHz HCSL differential reference clock compliant with PCI-SIG specifications. It sources timing from a 25 MHz crystal or clock input and delivers low-jitter output directly to PCIe root complexes and endpoints. Its design eliminates external termination and supports spread spectrum to reduce EMI-making SI52111-B6-GM2 ideal for compact, high-density PCIe implementations.

Does the SI52111-B6-GM2 require external termination resistors on its DIFF1 output?

No, the SI52111-B6-GM2 does not require external termination resistors on its DIFF1 output. Its integrated HCSL driver provides matched 50 Ω source impedance and is specified to drive standard PCIe loads directly. The datasheet confirms "No termination resistors required" and specifies output swing (300–550 mV), crossing point voltage, and slew rate under 50 Ω differential load conditions-validating SI52111-B6-GM2's self-terminating capability.

Can the SI52111-B6-GM2 operate with a 25 MHz clock input instead of a crystal?

Yes, the SI52111-B6-GM2 supports both 25 MHz crystal (via XIN/XOUT) and 25 MHz single-ended clock input (via XIN/CLKIN pin). When using an external clock, XOUT must be left floating. Input specifications-including VIH (≥2 V), VIL (≤0.8 V), duty cycle (45–55%), and cycle-to-cycle jitter (≤250 ps)-are defined for CLKIN operation. This dual-input flexibility makes SI52111-B6-GM2 adaptable to systems with existing clock trees or crystal-less architectures.

What is the significance of the "–0.5% spread" feature in the SI52111-B6-GM2?

The "–0.5% spread" refers to center-down spread spectrum modulation at 30–33 kHz, which reduces electromagnetic interference (EMI) by spreading the 100 MHz clock energy across a narrow band. This feature is exclusive to the SI52111-B6 variant and is validated for PCIe Gen 3 SRNS and Gen 4 compliance. Unlike fixed-frequency clocks, SI52111-B6-GM2 maintains timing margin while lowering peak spectral amplitude-critical for passing FCC/CE radiated emissions tests in compact consumer and networking hardware.

Is the SI52111-B6-GM2 pin-compatible with other members of the Si52111 family?

Yes, the SI52111-B6-GM2 is pin-compatible with SI52111-B5-GM2 (no spread) and shares identical 10-pin TDFN (3×3 mm) mechanical and electrical pinout-including VDD (pins 1,10), VSS (pins 4,5), XIN/CLKIN (pin 3), XOUT (pin 2), DIFF1 (pins 6,7), and NC (pins 8,9). This allows direct substitution in existing designs when spread spectrum is added later. However, SI52111-B6-GM2 is not pin-compatible with the 8-pin TSSOP variants (e.g., SI52111-B6-GT) due to differing pin count and layout.

SI52111-B6-GM2 Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 10-WFDFN Exposed Pad

Packaging:: Strip

Product Status:: Active

Programmable:: Not Verified

PLL:: Yes

Main Purpose:: PCI Express (PCIe)

Input:: Clock, Crystal

Output:: HCSL

Number of Circuits:: 1

Ratio - Input:Output:: 1:1

Differential - Input:Output:: No/Yes

Frequency - Max:: 100MHz

Voltage - Supply:: 2.97V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 10-TDFN (3x3)

SI52111-B6-GM2 FAQ

1.How can I place an order for SI52111-B6-GM2 through Aetrix?

Please submit a Request for Quotation (RFQ) for SI52111-B6-GM2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI52111-B6-GM2 reliable?

The price and inventory of SI52111-B6-GM2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI52111-B6-GM2 is usually 5 days.

3.What payment methods are accepted for SI52111-B6-GM2?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI52111-B6-GM2 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI52111-B6-GM2?

SI52111-B6-GM2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI52111-B6-GM2 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI52111-B6-GM2?

For technical support, including SI52111-B6-GM2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI52111-B6-GM2 requirements.

6.How does Aetrix verify that SI52111-B6-GM2 is sourced from the original manufacturer or authorized distributors?

All SI52111-B6-GM2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI52111-B6-GM2 meets industry standards.

7.What is the process for return or replacement of SI52111-B6-GM2?

All SI52111-B6-GM2 units undergo pre-shipment inspection (PSI). If there is an issue with SI52111-B6-GM2, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI52111-B6-GM2 part is unused and in its original packaging.

Return procedure for SI52111-B6-GM2:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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