Skyworks Solutions Inc. SI52146-A01AGMR

Overview

SI52146-A01AGMR from Skyworks Solutions is a PCIe Gen 1–4 compliant clock generator delivering six low-jitter, 0.7 V HCSL-compatible differential clock outputs from a 25 MHz crystal or clock input. It supports PCIe common clock and Gen 3 SRNS modes, features per-output enable pins, spread-spectrum control (–0.5% down-spread), and operates across –40 to +85 °C with 3.3 V supply. It is used in multi-lane PCIe systems requiring strict jitter compliance, such as network-attached storage controllers.

For engineers reviewing the SI52146-A01AGMR datasheet, SI52146-A01AGMR pinout, SI52146-A01AGMR application, or SI52146-A01AGMR equivalent, key selection criteria include PCIe Gen 4 phase jitter (≤0.6 ps RMS), 32-pin QFN package compatibility, I²C register readback capability, and independent OE control for each of six differential outputs.

Technical Context

The SI52146-A01AGMR integrates a high-stability PLL with configurable bandwidth (2–5 MHz) optimized for PCIe Gen 4 common clock timing, achieving ≤0.6 ps RMS phase jitter (10 kHz–Nyquist). Its architecture supports both crystal (25 MHz parallel-resonant AT-cut, 12–15 pF load) and single-ended clock inputs, with internal trim capacitor calculation support.

All six differential outputs are independently enabled via dedicated OE pins (OE_DIFF0–OE_DIFF5) and share a single SSON pin for triangular spread-spectrum modulation at 31.5 kHz (±1.5 kHz). Power-down is managed through the dual-function CKPWRGD/PDB pin, which transitions from power-good monitoring to asynchronous active-low shutdown after initial sampling.

Key Specifications

Pinout & Package

SI52146-A01AGMR is housed in a 5 mm × 5 mm, 32-pin QFN package with exposed thermal pad (Mo-220 standard). Pin pitch is 0.5 mm; recommended land pattern follows IPC-7351 with NSMD pads and 0.125 mm stencil thickness.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with IDT8T49N242A and ICS843002AGI, the SI52146-A01AGMR uniquely delivers Gen 4-compliant jitter, six independently controllable outputs, and integrated spread-spectrum control in a compact 5×5 mm QFN-making it optimal for space-constrained, high-speed storage and networking platforms.

Availability

SI52146-A01AGMR is available at Aetrix Electronics and suitable for network-attached storage, enterprise switching, and wireless infrastructure applications requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature performance.

Supply support for SI52146-A01AGMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si52146 product line was designed specifically for PCIe timing in high-density, thermally constrained systems-delivering Gen 4 compliance, low power, and flexible control in minimal footprint.

FAQ

What PCIe generations does the SI52146-A01AGMR support?

The SI52146-A01AGMR supports PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS, and Gen 4 common clock specifications per PCI-SIG Base Specification 4.0 rev 0.5. Its measured phase jitter is ≤0.6 ps RMS for Gen 4 (10 kHz–Nyquist), ≤0.6 ps for Gen 3 common clock, and ≤0.42 ps for Gen 3 SRNS-ensuring full compliance across all targeted generations. The SI52146-A01AGMR achieves this using a configurable PLL with 2–5 MHz bandwidth and optimized loop filter design.

Does the SI52146-A01AGMR require external termination resistors on its differential outputs?

No, the SI52146-A01AGMR provides low-power push-pull HCSL-compatible outputs with 0.7 V differential swing and built-in current sources, eliminating the need for external 50 Ω termination resistors. This simplifies PCB layout, reduces component count, and improves signal integrity by avoiding stub effects. The SI52146-A01AGMR's outputs meet PCIe AC timing requirements-including crossing point voltage (VOX = 300–550 mV) and slew rate (1–8 V/ns)-without external components.

How is spread spectrum controlled on the SI52146-A01AGMR?

Spread spectrum on the SI52146-A01AGMR is controlled via the SSON pin: when driven high, it enables a triangular –0.5% down-spread at 31.5 kHz (±1.5 kHz). The SI52146-A01AGMR uses an internal modulator; no external components are required. This feature reduces peak radiated emissions while maintaining PCIe link stability, as confirmed by Skyworks' PCIe Clock Jitter Tool validation. The SI52146-A01AGMR's spread profile is fixed and cannot be adjusted in frequency or depth via I²C.

Can the SI52146-A01AGMR operate with a 25 MHz clock input instead of a crystal?

Yes, the SI52146-A01AGMR accepts either a 25 MHz parallel-resonant crystal (XIN mode) or a 25 MHz CMOS-level clock signal (CLKIN mode) on the XIN/CLKIN pin. In CLKIN mode, the SI52146-A01AGMR requires VIH ≥2.0 V and VIL ≤0.8 V, with duty cycle 47–53% and cycle-to-cycle jitter ≤250 ps. The SI52146-A01AGMR automatically detects input type and configures internal circuitry accordingly-no configuration register changes are needed.

What is the function of the CKPWRGD/PDB pin on the SI52146-A01AGMR?

The CKPWRGD/PDB pin on the SI52146-A01AGMR serves two sequential roles: during initial power-up, it acts as CKPWRGD (clock power-good) to indicate valid supply and clock; once sampled high, it becomes PDB (power-down) - an asynchronous active-low input that disables all outputs, crystal oscillator, and I²C logic in a glitch-free manner. The SI52146-A01AGMR includes a 100 kΩ internal pull-up, so the pin must be actively driven for reliable operation.