Skyworks Solutions Inc. SI52202-A01BGMR

Overview

SI52202-A01BGMR from Skyworks Solutions is a 2-output, 100 MHz PCIe Gen 1–7 and SRIS-compliant clock generator with LP-HCSL differential outputs, 0.085 ps RMS jitter, 1.5–1.8 V dual-supply operation (VDD/VDD_IO), and –40 to +85 °C industrial temperature range. It serves as the primary timing source for PCIe root complexes and endpoints in compact add-in cards and embedded systems.

For engineers reviewing the SI52202-A01BGMR datasheet, SI52202-A01BGMR pinout, SI52202-A01BGMR application, or SI52202-A01BGMR equivalent, key selection criteria include its 20-pin QFN (3 × 3 mm) footprint, hardware- and I²C-controllable output enable/spread-spectrum, and absence of REF output-critical for space-constrained, low-power PCIe timing designs.

Technical Context

The SI52202-A01BGMR integrates a PLL with spread-spectrum control (–0.25% or –0.5% down-spread), supports only 100 MHz differential output (no 133/200 MHz option), and omits both the REF LVCMOS output and PWRDNb Wake-on-LAN functionality present in higher-pin-count family members. Its architecture targets minimal board area and power in 2-output PCIe timing nodes.

It accepts a 25 MHz crystal or clock input, uses push-pull LP-HCSL drivers with internal 100 Ω line matching, and provides individual OEb pins for each of its two differential pairs-enabling per-output power gating without I²C interaction. All control pins feature internal pull-up/pull-down resistors for robust default behavior.

Key Specifications

Pinout & Package

SI52202-A01BGMR is housed in a 20-pin QFN package (3 mm × 3 mm, 0.5 mm pitch) with exposed thermal pad. Pin 1 is at top-left corner adjacent to notch/dot marking; ground pad must be soldered to PCB ground plane via multiple vias for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock generator applications.

Compared with SI52204-A01AGM, SI52202-A01BGMR trades output count and REF clock for 40% smaller footprint and lower power; versus ICS843002AGI-01LFT, it delivers Gen 7 readiness, spread spectrum, and modern 1.5 V operation at the cost of package compatibility.

Availability

SI52202-A01BGMR is available at Aetrix Electronics and suitable for PCIe add-in cards, embedded root complexes, and network interface cards requiring stable component supply, long-term lifecycle support, and RoHS-6 compliance.

Supply support for SI52202-A01BGMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and connectivity solutions for high-performance wireless and wired infrastructure.

The Si522xx family was designed specifically for PCI Express Gen 1–7 timing requirements, emphasizing ultra-low jitter, spread-spectrum EMI reduction, and minimal footprint across scalable output counts-from 2 to 12 channels.

FAQ

What is the maximum PCIe generation supported by the SI52202-A01BGMR?

The SI52202-A01BGMR is fully compliant with PCIe Gen 1 through Gen 7 common clock and SRIS architectures. Its 0.085 ps RMS jitter meets the stringent Gen 6 specification with design margin, ensuring reliable operation in next-generation high-speed interconnects. SI52202-A01BGMR does not require derating for Gen 7 deployment in standard board environments.

Does the SI52202-A01BGMR provide a 25 MHz LVCMOS reference clock output?

No, the SI52202-A01BGMR does not include a 25 MHz LVCMOS reference clock output. Unlike the Si52204/Si52208/Si52212 variants, this 2-output variant omits the REF/SA pin functionality entirely. SI52202-A01BGMR is optimized for applications where only differential PCIe clocks are required, reducing pin count and package size.

Can the SI52202-A01BGMR generate 133 MHz or 200 MHz output frequencies?

No, the SI52202-A01BGMR is factory-configured for 100 MHz differential outputs only. The FS pin has no effect on output frequency in this variant. Skyworks explicitly states that 133 MHz or 200 MHz operation requires contacting the factory-no standard SI52202-A01BGMR unit supports those frequencies. SI52202-A01BGMR is strictly a 100 MHz PCIe timing device.

What is the purpose of the VDD_IO pin on the SI52202-A01BGMR?

The VDD_IO pin supplies power exclusively to the LP-HCSL output drivers on the SI52202-A01BGMR, operating over 1.05–1.5 V. This separate rail isolates output switching noise from the core PLL and analog circuitry, improving jitter performance and enabling optimization of drive strength. SI52202-A01BGMR requires independent regulation or filtering of VDD_IO for best signal integrity.

Is Wake-on-LAN functionality supported on the SI52202-A01BGMR?

No, Wake-on-LAN is not supported on the SI52202-A01BGMR. The PWRGD/PWRDNb pin functions solely as an active-low power-down control and lacks the internal logic to maintain REF or auxiliary clocks during sleep-unlike the Si52204/Si52208/Si52212 variants. SI52202-A01BGMR disables all outputs completely when PWRDNb is asserted.