Skyworks Solutions Inc. SI5310-BM

Overview

SI5310-BM from Silicon Laboratories is a precision clock multiplier and regenerator IC implementing DSPLL® architecture. It accepts 9.4–668 MHz differential or single-ended input clocks, generates clean 150–167 MHz or 600–668 MHz multiplied outputs, and delivers jitter-attenuated 1×CLKIN regeneration - all from a single 2.5 V supply across –40 to +85 °C. Used in SONET/SDH line cards for jitter-cleansing and frequency translation.

For engineers reviewing the SI5310-BM datasheet, SI5310-BM pinout, SI5310-BM application, or SI5310-BM equivalent, key selection criteria include its dual-mode multiplication (150–167 MHz / 600–668 MHz), sub-0.5 psrms jitter generation at 622 MHz, DSPLL-based jitter attenuation without analog loop filters, and 20-pin 4×4 mm MLP package with differential CML I/Os.

Technical Context

The SI5310-BM integrates a digital signal-processing PLL (DSPLL®) that replaces analog loop filters with deterministic DSP algorithms, enabling stable jitter transfer bandwidths from 19 kHz to 1.68 MHz depending on MULTSEL and input frequency. Its phase detector compares CLKIN against a divided-down VCO output while REFCLK provides lock reference - automatically detected across five integer multiples of CLKIN.

It supports two independent clock paths: MULTOUT (integer-multiplied output) and CLKOUT (1× jitter-cleaned output), both synchronized to rising edges of MULTOUT. The device uses external 10 kΩ REXT for bias current calibration and features loss-of-lock (LOL) detection with ±300 ppm lock-in and ±600 ppm loss thresholds.

Key Specifications

Pinout & Package

SI5310-BM is housed in a 20-pin, 4×4 mm micro leadframe package (MLP) with exposed thermal pad. Pin 1 is top-left corner (CLKOUT+), pin 20 is bottom-right (VDD); GND pad occupies center-bottom of underside and must be soldered to PCB ground plane.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock multiplier and regenerator applications.

Compared with Si5315-B-GM and ICS853S01I, the SI5310-BM uniquely balances low-jitter regeneration, dual-output capability, and DSPLL-based filterless design - making it optimal for space-constrained telecom modules needing deterministic jitter attenuation without added complexity or power overhead.

Availability

SI5310-BM is available at Aetrix Electronics and suitable for SONET/SDH systems, terabit routers, and optical transceiver modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for SI5310-BM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in timing, wireless, and sensor technologies for communications, computing, and industrial markets.

The SI5310-BM belongs to Silicon Labs' precision clock IC product line, engineered specifically for telecom infrastructure applications demanding ultra-low jitter, small form factor, and robust jitter tolerance in harsh thermal environments.

FAQ

What is the primary function of the SI5310-BM in a clock tree?

The SI5310-BM serves as a dual-path precision clock conditioner: it simultaneously multiplies an input clock to either 150–167 MHz or 600–668 MHz (via MULTOUT) while regenerating a jitter-attenuated 1× replica (CLKOUT). This enables systems to distribute clean, synchronized clocks to multiple high-speed SerDes lanes without cascading jitter. Its DSPLL® architecture ensures consistent performance across temperature and voltage variations.

Does the SI5310-BM require an external crystal or oscillator?

No, the SI5310-BM does not require an external crystal. It operates from an external differential or single-ended clock input (CLKIN) and uses an internal DSPLL® to synthesize outputs. However, it does require an external reference clock (REFCLK) - which can be derived from CLKIN - to maintain PLL lock integrity and enable loss-of-lock detection.

How does the MULTSEL pin affect SI5310-BM operation?

The MULTSEL pin configures the SI5310-BM's output frequency range: logic-low selects the 600–668 MHz MULTOUT range (e.g., 622.08 MHz for SONET OC-48), while logic-high selects 150–167 MHz (e.g., 155.52 MHz for OC-12). This pin also determines internal divider ratios and corresponding jitter transfer bandwidths - directly impacting system-level jitter filtering behavior.

Can the SI5310-BM regenerate a clock without multiplication?

Yes, the SI5310-BM supports 1× multiplication mode - where CLKOUT delivers a jitter-attenuated, duty-cycle-corrected version of CLKIN while MULTOUT remains inactive. In this mode, the device functions purely as a clock regenerator. Note that CLKOUT is invalid when MULTOUT is configured for 1×CLKIN output, per datasheet Table 9 Note 2.

What is the role of the REXT pin on the SI5310-BM?

The REXT pin connects to a 10 kΩ (1%) resistor tied to GND, setting internal bias currents for the DSPLL® core. This external resistor enables precise current control - reducing power consumption and improving jitter consistency versus internal resistor-based designs. Omitting or misvaluing REXT degrades jitter performance and may cause calibration failure during PWRDN/CAL assertion.