Skyworks Solutions Inc. SI5315A-C-GM

Overview

SI5315A-C-GM from Skyworks Solutions is a jitter-attenuating synchronous Ethernet/telecom clock multiplier IC supporting ITU-T G.8262 EEC Options 1 and 2. It accepts dual differential or single-ended inputs (8 kHz–644.53 MHz), generates two equal-frequency low-jitter outputs (8 kHz–644.53 MHz), and implements third-generation DSPLL® with user-programmable loop bandwidth (60–8.4 kHz) for telecom line card timing in 10G LAN SyncE, SONET OC-48, and T1/E1 systems.

For engineers reviewing the SI5315A-C-GM datasheet, SI5315A-C-GM pinout, SI5315A-C-GM application, or SI5315A-C-GM equivalent, this page delivers verified specifications including ultra-low RMS jitter (0.23 ps @ 1.875–20 MHz), LVPECL/LVDS/CML/CMOS output format selection, hitless input switching, holdover mode, and 36-QFN package compatibility - all critical for Synchronous Ethernet equipment slave clock design.

Technical Context

The SI5315A-C-GM integrates a third-generation DSPLL® core with dual-input arbitration logic, programmable loop bandwidth control via BWSEL[1:0], and automatic/manual hitless switching between CKIN1 and CKIN2. Its PLL architecture supports wander filtering when paired with a Stratum 3-compliant timing card, enabling compliance with ITU-T G.8262 EEC Option 1 and 2 requirements.

It features on-chip voltage regulation with high PSRR, loss-of-signal (LOS1/LOS2) and loss-of-lock (LOL) status indicators, and configurable output signal formats per SFOUT[1:0]. The device operates across –40 to +85 °C with single-supply support (1.8 V/2.5 V/3.3 V) and includes holdover frequency historical averaging (6.7 sec) and delay (26.2 ms) for stable timing during input failure.

Key Specifications

Pinout & Package

The SI5315A-C-GM is housed in a 6 × 6 mm, 36-pin QFN package with exposed thermal pad. Pin assignments are fully defined in Skyworks' Rev. 1.0 datasheet (pages 10, 43–44), supporting standard PCB land patterns (page 50) and top marking per section 14.1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock multiplier applications.

Compared with Si5317A-C-GM and LMK04828BISQE/NOPB, the SI5315A-C-GM provides the most direct path to ITU-T G.8262 EEC Option 1/2 compliance with minimal BOM count, no firmware, and deterministic pin-controlled configuration - making it ideal for high-volume, carrier-class Synchronous Ethernet line cards where reliability and qualification speed are critical.

Availability

SI5315A-C-GM is available at Aetrix Electronics and suitable for synchronous Ethernet line cards, SONET OC-48 timing modules, and T1/E1 line card designs requiring stable component supply, long-term lifecycle support, and full traceability.

Supply support for SI5315A-C-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The SI5315A-C-GM belongs to Skyworks' DSPLL® timing family, engineered specifically for telecom and carrier Ethernet applications requiring ITU-T G.8262-compliant jitter attenuation, hitless redundancy, and simplified system-level clock architecture.

FAQ

What is the maximum output frequency supported by the SI5315A-C-GM?

The SI5315A-C-GM supports a maximum output frequency of 644.53 MHz for LVPECL, LVDS, and CML formats. In CMOS format, the maximum output frequency is limited to 161.13 MHz. This specification is confirmed in Table 3 (AC Characteristics) of the Skyworks Rev. 1.0 datasheet, and applies to the SI5315A speed grade referenced in the SI5315A-C-GM ordering code.

Does the SI5315A-C-GM support ITU-T G.8262 Synchronous Ethernet compliance?

Yes, the SI5315A-C-GM supports ITU-T G.8262 Equipment Clock (EEC) Options 1 and 2 when paired with a timing card that implements the required wander filter and provides a Stratum 3-compliant reference clock. This capability is explicitly stated in the device description, features list, and System Level Overview sections of the official Skyworks datasheet for SI5315A-C-GM.

How does the SI5315A-C-GM implement hitless clock switching between its two inputs?

The SI5315A-C-GM performs hitless switching by continuously monitoring phase alignment between the selected input and internal feedback paths, then executing phase-matched transitions with typical output phase transients under 200 ps. This behavior is enabled by its third-generation DSPLL® architecture and is validated in functional testing per ITU-T G.8262 and Telcordia GR-253-CORE requirements - a key feature documented for SI5315A-C-GM in Section 4.1 and Figure 6 of the datasheet.

What output signal formats does the SI5315A-C-GM support, and how are they configured?

The SI5315A-C-GM supports LVPECL, LVDS, CML, and CMOS output formats, selected via the SFOUT[1:0] pins (pins 26 and 27). These are hardwired three-level (L/M/H) inputs, allowing configuration without I²C or SPI. Format selection is fixed at power-up and affects drive strength, common-mode voltage, and swing - details are specified in Table 2 (DC Characteristics) and Section 6.2 of the SI5315A-C-GM datasheet.

Is an external crystal required for the SI5315A-C-GM to operate?

No, an external crystal is optional. The SI5315A-C-GM can operate using either a 40 MHz fundamental-mode crystal connected to XA/XB pins or an external clock source applied to the same pins. The device includes internal oscillator circuitry and supports both configurations - as confirmed in the "Crystal/Reference Clock Input" section (page 38) and Functional Block Diagram of the SI5315A-C-GM datasheet.