Skyworks Solutions Inc. SI5317C-C-GMR

Overview

SI5317C-C-GMR from Skyworks Solutions is a pin-controlled 1:1 jitter cleaning clock IC designed for high-performance timing applications requiring sub-1 ps jitter attenuation without multiplication. It accepts a single 1–711 MHz differential or single-ended clock input and generates two low-jitter LVPECL/LVDS/CML/CMOS outputs at identical frequency, with user-selectable loop bandwidth (60 Hz–8.4 kHz) and on-chip DSPLL® technology eliminating external VCXO and loop filter components.

For engineers reviewing the SI5317C-C-GMR datasheet, SI5317C-C-GMR pinout, SI5317C-C-GMR application, or SI5317C-C-GMR equivalent, this device is critical in systems demanding GR-253-CORE–compliant jitter performance, precise skew control via INC/DEC pins, loss-of-signal/loss-of-lock alarms, and VCO freeze during input failure-especially where board space, supply simplicity (1.8/2.5/3.3 V), and thermal robustness (–40 to +85 °C) are constrained.

Technical Context

The SI5317C-C-GMR implements Skyworks' third-generation DSPLL® architecture with fully integrated voltage-controlled oscillator and high-PSRR on-chip regulator, enabling jitter attenuation across its full 1–711 MHz input/output range without external frequency references. Its loop bandwidth is digitally set via BWSEL[1:0] pins using a three-level logic interface (High/Mid/Low), mapping directly to six discrete bandwidth options from 60 Hz to 8.4 kHz per frequency plan table.

Functional operation includes real-time LOS/LOL monitoring with dedicated output alarms, VCO freeze mode that sustains stable output using XA/XB crystal reference upon input loss, and programmable output skew adjustment (±0.21 ns step) via edge-triggered INC/DEC pins synchronized to the selected loop bandwidth. All outputs support format selection (LVPECL, LVDS, CML, CMOS) with defined drive strength, common-mode, and swing specifications per load type.

Key Specifications

Pinout & Package

SI5317C-C-GMR is housed in a 36-pin QFN package (6 mm × 6 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined by three-level logic (VDD, GND, or floating ≈ VDD/2) for configuration inputs, enabling flexible hardware-based setup without I²C or SPI.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter cleaning clock applications.

Compared with Si5317B-C-GMR, the SI5317C-C-GMR provides identical jitter performance and pin compatibility but targets different frequency plan segments; versus LMK04828BISQE/NOPB, it trades SPI configurability and dual-loop capability for zero-firmware operation and 36-QFN space savings - making it optimal for cost-sensitive, high-volume telecom and medical OEM designs.

Availability

SI5317C-C-GMR is available at Aetrix Electronics and suitable for wireless infrastructure, SONET/SDH line cards, and medical ultrasound systems requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5317C-C-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications, automotive, and industrial markets.

The Si5317 product line delivers pin-configurable jitter cleaning clocks for high-reliability timing applications where minimal external components, deterministic performance, and GR-253-CORE compliance are mandatory.

FAQ

What is the maximum input frequency supported by the SI5317C-C-GMR?

The SI5317C-C-GMR supports an input frequency range of 1 MHz to 711 MHz, verified across all output formats and supply voltages (1.8 V, 2.5 V, 3.3 V). This range is confirmed in Table 4 of the official Skyworks datasheet Rev. 1.1, with test conditions specifying valid operation up to 711 MHz for both CKIN and CKOUT signals under recommended operating conditions.

Does the SI5317C-C-GMR require external loop filter components?

No, the SI5317C-C-GMR does not require external loop filter components. Its third-generation DSPLL® architecture integrates the VCO, charge pump, and loop filter functions on-die, eliminating the need for external capacitors or resistors - a key differentiator confirmed in the "Description" and "Features" sections of the Skyworks Si5317 datasheet Rev. 1.1.

How does the VCO freeze feature operate in the SI5317C-C-GMR?

When the SI5317C-C-GMR detects loss of signal (LOS) on CKIN, it activates VCO freeze mode: the DSPLL latches its current VCO control settings and switches to using the XA/XB crystal or reference clock as its timing source, sustaining stable output clocks without interruption - a behavior explicitly documented in Section 2.1 and Section 3.5 of the Si5317 datasheet Rev. 1.1.

Can the SI5317C-C-GMR generate CMOS outputs at 622.08 MHz?

No, the SI5317C-C-GMR cannot generate CMOS outputs at 622.08 MHz. Its maximum CMOS output frequency is 212.5 MHz, as specified in Table 4 (AC Characteristics) of the Skyworks datasheet Rev. 1.1. At 622.08 MHz, only LVPECL, LVDS, or CML output formats are supported.

What is the typical jitter performance of the SI5317C-C-GMR at 622.08 MHz?

The SI5317C-C-GMR achieves 300 fs rms typical jitter (12 kHz–20 MHz integration band) at 622.08 MHz with LVPECL outputs and 120 Hz loop bandwidth, as stated in the "Features" section and validated in Table 5 (Performance Specifications) of the Skyworks Si5317 datasheet Rev. 1.1 - meeting GR-253-CORE requirements for OC-192 applications.