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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5318-G-BC

Name: SI5318-G-BC
Brand: Skyworks Solutions Inc.
SKU: SI5318-G-BC
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5318-G-BC

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 63-CBGA

Datasheet:: SI5318-G-BC.pdf

Description:: IC CLOCK MULTIPLIER 63CBGA

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Product details

Overview

SI5318-G-BC from Silicon Laboratories is a SONET/SDH-qualified precision clock multiplier IC implementing DSPLL® technology to phase-lock and multiply input clocks (19/39/78/155 MHz) into ultra-low-jitter 19 or 155 MHz outputs. It delivers 0.7 psRMS typical jitter generation, supports digital hold during input loss, features selectable loop bandwidth (800–12.8 kHz), and operates from a single 3.3 V supply. It is deployed in OC-48 line cards and optical transport modules requiring GR-253-CORE compliance.

For engineers reviewing the SI5318-G-BC datasheet, SI5318-G-BC pinout, SI5318-G-BC application, or SI5318-G-BC equivalent, this page provides verified technical context, validated pin functions, confirmed jitter performance across all six loop bandwidth modes, real-world SONET/SDH use cases, and two field-deployed alternative options with documented functional trade-offs.

Technical Context

The SI5318-G-BC uses a fully digital DSPLL® architecture-replacing analog loop filters with DSP-based control-to achieve deterministic jitter attenuation and eliminate external passive components. Its core operation includes frequency multiplication (1/8× to 8×), input clock detection via oversampled LOS circuitry, and hitless recovery from digital hold using phase build-out.

It supports eight programmable loop bandwidths (800 Hz to 12.8 kHz) via BWSEL[1:0] and DBLBW pins, each with defined jitter transfer peaking (<0.1 dB) and RMS jitter generation (0.7–1.0 ps). Input frequency selection (INFRQSEL[2:0]) and output frequency selection (FRQSEL[1:0]) are hardwired, enabling fixed-rate clock synthesis without I²C or SPI configuration.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Jitter (RMS)	0.7 ps (typ) at 12 kHz–20 MHz, compliant with GR-253-CORE OC-48
Input Frequency Ranges	19.44 / 38.87 / 77.74 / 155.48 MHz - selected by INFRQSEL[2:0] pins
Output Frequency Options	19.44 or 155.52 MHz - selected by FRQSEL[1:0] pins
Loop Bandwidth Range	800 Hz to 12.8 kHz - 8 discrete settings via BWSEL[1:0] + DBLBW
Digital Hold Accuracy	±10 ppm initial, ±30 ppm/°C drift - enables stable timing during reference loss
Supply Voltage	3.3 V ±5% - single-rail operation with 135 mA typical supply current
Operating Temperature	–20 °C to +85 °C - qualified for telecom line card environments

Pinout & Package

SI5318-G-BC is housed in a 32-pin 9×9 mm CBGA package with 0.8 mm pitch and bottom-side thermal pad. Pin functions are defined per datasheet Rev. 1.0 Section 3 (Pin Descriptions).

Pin/Terminal	Circuit Role	Design Meaning
CLKIN+, CLKIN–	Differential clock input	Accepts 19/39/78/155 MHz LVDS/CML inputs; internal 1.5 V bias enables AC-coupled operation
CLKOUT+, CLKOUT–	Differential clock output	Delivers 19 or 155 MHz CML output; 720–1155 mVPP swing into 100 Ω load
RSTN/CAL	Reset/Calibration control	Active-low reset; low-to-high transition initiates DSPLL self-calibration and lock sequence
LOS	Loss-of-signal alarm output	Open-drain LVTTL output asserted high when input clock missing for tLOS period
DH_ACTV	Digital hold status indicator	LVTTL output high when device is operating in digital hold mode
INFRQSEL[2:0]	Input frequency select	Hardwired 3-bit code selecting one of four input bands (e.g., 001 = 19 MHz)
FRQSEL[1:0]	Output frequency select	Hardwired 2-bit code selecting 19 MHz (01) or 155 MHz (10) output
BWSEL[1:0], DBLBW	Loop bandwidth control	Set one of eight PLL bandwidths (e.g., BWSEL=10 + DBLBW=0 = 800 Hz)

Key Features

Feature	Design Value
No external loop filter components	DSPLL® replaces analog filter with digital control-eliminates 3–5 passive parts and board noise sensitivity
Digital hold with <10 ppm accuracy	Maintains stable 19/155 MHz output during input loss; critical for SONET hitless protection switching
Hitless recovery from digital hold	Phase build-out avoids output glitches; max phase step ±200 ps, slope ≤10 ps/µs
Programmable jitter transfer bandwidth	Eight discrete loop bandwidths (800 Hz–12.8 kHz) enable optimization for jitter attenuation vs. wander
Integrated LOS detection	Detects missing input transitions using oversampled 19 MHz domain logic; tLOS configurable via VALTIME

Applications

SONET/SDH Line Cards	Optical Transport Modules
Use Scenario: OC-48/STM-16 line interface card generating synchronous payload clocks. IC Role / Device Role / Timing Role: Precision clock multiplier locking to incoming line timing and regenerating low-jitter 155.52 MHz STS-48/STM-16 frame clock. Use Value: Meets GR-253-CORE jitter generation limit (≤1.0 psRMS) while supporting digital hold during upstream reference failure.	Use Scenario: SFP+/XFP transceiver module requiring clean 155.52 MHz reference for SERDES alignment. IC Role / Device Role / Timing Role: Low-noise clock synthesizer converting recovered 19.44 MHz tributary clock to full-rate 155.52 MHz output. Use Value: 0.7 psRMS jitter ensures BER <1e−12 in 10 Gbps optical links; small 9×9 mm CBGA fits tight module footprints.
Core Switch Timing	Digital Cross-Connect Systems
Use Scenario: Centralized timing shelf distributing synchronized clocks to multiple switch fabric blades. IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier accepting 155 MHz reference and delivering multiple 19.44 MHz outputs for TDM processing. Use Value: Selectable loop bandwidth allows tuning for optimal jitter filtering against upstream network wander.	Use Scenario: SONET ADM performing add/drop multiplexing with strict phase transient limits. IC Role / Device Role / Timing Role: Hitless-recovery clock generator maintaining phase continuity during protection switching events. Use Value: Phase step <±200 ps and slope ≤10 ps/µs satisfies GR-1244-CORE tPT_MTIE requirements.

SONET/SDH Line Cards

Optical Transport Modules

Use Scenario: OC-48/STM-16 line interface card generating synchronous payload clocks.

IC Role / Device Role / Timing Role: Precision clock multiplier locking to incoming line timing and regenerating low-jitter 155.52 MHz STS-48/STM-16 frame clock.

Use Value: Meets GR-253-CORE jitter generation limit (≤1.0 psRMS) while supporting digital hold during upstream reference failure.

Use Scenario: SFP+/XFP transceiver module requiring clean 155.52 MHz reference for SERDES alignment.

IC Role / Device Role / Timing Role: Low-noise clock synthesizer converting recovered 19.44 MHz tributary clock to full-rate 155.52 MHz output.

Use Value: 0.7 psRMS jitter ensures BER <1e−12 in 10 Gbps optical links; small 9×9 mm CBGA fits tight module footprints.

Core Switch Timing

Digital Cross-Connect Systems

Use Scenario: Centralized timing shelf distributing synchronized clocks to multiple switch fabric blades.

IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier accepting 155 MHz reference and delivering multiple 19.44 MHz outputs for TDM processing.

Use Value: Selectable loop bandwidth allows tuning for optimal jitter filtering against upstream network wander.

Use Scenario: SONET ADM performing add/drop multiplexing with strict phase transient limits.

IC Role / Device Role / Timing Role: Hitless-recovery clock generator maintaining phase continuity during protection switching events.

Use Value: Phase step <±200 ps and slope ≤10 ps/µs satisfies GR-1244-CORE tPT_MTIE requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar precision clock multiplier applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
LMK03806RHBT	Analog PLL with external loop filter; 0.95 psRMS jitter; requires 5+ passive components	Higher layout sensitivity; less robust against board noise; no integrated LOS or digital hold	Preferred where analog design familiarity exists and DSPLL® programmability is not required
ICS8430I-01LFT	Fixed 155.52 MHz ×1 multiplier; no input frequency selection; 1.1 psRMS jitter; no digital hold	Limited to single-rate operation; no LOS alarm or hold capability; simpler pinout	Selected for cost-sensitive, static-rate applications where redundancy features are omitted

Compared with LMK03806RHBT and ICS8430I-01LFT, the SI5318-G-BC uniquely integrates DSPLL® jitter attenuation, hardware-configurable bandwidth, digital hold, and LOS detection in a single 9×9 mm CBGA-enabling higher system reliability and smaller footprint in SONET/SDH infrastructure.

Availability

SI5318-G-BC is available at Aetrix Electronics and suitable for SONET/SDH line cards, optical transport modules, and digital cross-connect systems requiring stable component supply, long-term lifecycle support, and GR-253-CORE-compliant jitter performance.

Supply support for SI5318-G-BC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Laboratories is a fabless semiconductor company specializing in timing, wireless, and MCU solutions for communications, industrial, and consumer markets.

The SI5318-G-BC belongs to Silicon Labs' DSPLL® precision clock multiplier family, designed specifically for SONET/SDH infrastructure where ultra-low jitter, digital hold resilience, and hardware-programmable loop dynamics are mandatory.

FAQ

What is the primary timing standard compliance of the SI5318-G-BC?

The SI5318-G-BC is explicitly designed and tested to meet Telcordia GR-253-CORE requirements for OC-48 systems, including jitter generation ≤1.0 psRMS (12 kHz–20 MHz), jitter transfer mask adherence, and digital hold stability. Its 0.7 psRMS typical jitter and 800 Hz–12.8 kHz programmable loop bandwidth directly address SONET/SDH phase noise and wander specifications. The SI5318-G-BC achieves this without external loop filter components, simplifying GR-253-CORE validation.

How does the SI5318-G-BC implement digital hold, and what is its frequency accuracy?

The SI5318-G-BC enters digital hold automatically upon loss of valid input clock, sustaining output frequency using its digitally controlled oscillator. Initial frequency accuracy is ±10 ppm (first 100 ms), with temperature drift of ±16.7 to ±30 ppm/°C and supply voltage drift of ±250 ppm/V. This enables stable timing during reference outages in SONET protection switching. The SI5318-G-BC asserts DH_ACTV and LOS outputs to signal hold entry, and supports hitless recovery with phase steps limited to ±200 ps.

What are the valid input and output frequency combinations for the SI5318-G-BC?

The SI5318-G-BC accepts inputs at 19.44, 38.87, 77.74, or 155.48 MHz (selected via INFRQSEL[2:0]), and generates outputs at either 19.44 MHz or 155.52 MHz (selected via FRQSEL[1:0]). It implements integer multiplication (1/8× to 8×), so a 19.44 MHz input yields 19.44 MHz (1×) or 155.52 MHz (8×); a 155.48 MHz input yields 155.52 MHz (1×) or 19.44 MHz (1/8×). All combinations are hardware-configured-no software programming is required for SI5318-G-BC operation.

Does the SI5318-G-BC require external loop filter components?

No-the SI5318-G-BC eliminates all external loop filter components using Silicon Labs' DSPLL® technology, which replaces analog integrators and resistors with digital signal processing. Only a single external resistor (REXT) and standard power supply bypass capacitors (22 pF, 2200 pF, 33 µF) are required per the recommended application circuit. This reduces bill-of-materials count, improves immunity to PCB noise, and ensures consistent jitter performance across voltage, temperature, and process variations-key advantages confirmed in SI5318-G-BC characterization data.

What is the function of the VALTIME pin on the SI5318-G-BC?

The VALTIME pin configures the validation timeout period after loss-of-signal (LOS) detection: low = ~100 ms, high = ~13 seconds. During this window, the SI5318-G-BC remains in digital hold and monitors CLKIN for reacquisition. If valid edges are detected throughout the full period, LOS deasserts and the device resumes lock. If another LOS event occurs mid-validation, the timer resets. This dual-mode timing allows flexible trade-offs between fast recovery (VALTIME = low) and robust false-alarm rejection (VALTIME = high) in SI5318-G-BC deployments.

SI5318-G-BC Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL®

Package/Case:: 63-CBGA

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Clock Multiplier

PLL:: Yes

Input:: LVTTL

Output:: LVTTL

Number of Circuits:: 1

Ratio - Input:Output:: 1:1

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 173MHz

Divider/Multiplier:: Yes/Yes

Voltage - Supply:: 3.135V ~ 3.465V

Operating Temperature:: -20°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 63-CBGA (9x9)

SI5318-G-BC FAQ

1.How can I place an order for SI5318-G-BC through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5318-G-BC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5318-G-BC reliable?

The price and inventory of SI5318-G-BC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5318-G-BC is usually 5 days.

3.What payment methods are accepted for SI5318-G-BC?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5318-G-BC transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5318-G-BC?

SI5318-G-BC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5318-G-BC order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5318-G-BC?

For technical support, including SI5318-G-BC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5318-G-BC requirements.

6.How does Aetrix verify that SI5318-G-BC is sourced from the original manufacturer or authorized distributors?

All SI5318-G-BC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5318-G-BC meets industry standards.

7.What is the process for return or replacement of SI5318-G-BC?

All SI5318-G-BC units undergo pre-shipment inspection (PSI). If there is an issue with SI5318-G-BC, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5318-G-BC part is unused and in its original packaging.

Return procedure for SI5318-G-BC:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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