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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5322-C-GMR

Name: SI5322-C-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5322-C-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5322-C-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 36-VFQFN Exposed Pad

Datasheet:: SI5322-C-GMR.pdf

Description:: IC CLOCK MULTIPLIER 36QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5322-C-GMR from Skyworks Solutions is a pin-programmable precision clock multiplier IC for high-speed communication timing systems. It accepts dual 19.44–707 MHz differential inputs and generates two synchronized 19.44–1050 MHz outputs with jitter as low as 0.47 psRMS (50 kHz–80 MHz), supporting SONET OC-48/OC-192, 10GbE, and Fibre Channel line cards.

For engineers reviewing the SI5322-C-GMR datasheet, SI5322-C-GMR pinout, SI5322-C-GMR application, or SI5322-C-GMR equivalent, this page provides verified specifications, validated pin functions, confirmed DSPLL® loop bandwidth control (150 kHz–1.3 MHz), and real-world use cases in optical transport and datacom timing subsystems.

Technical Context

The SI5322-C-GMR implements Skyworks' third-generation DSPLL® architecture, enabling any-frequency synthesis without external VCXO or loop filter components. Its digitally selectable loop bandwidth (150 kHz to 1.3 MHz) allows jitter optimization per application, and dual-input loss-of-signal detection triggers automatic clock switching or digital hold mode.

It supports pin-programmed frequency tables (SONET/SDH, datacom, or SONET-to-datacom), three-level input logic (L/M/H) for FRQTBL, BWSEL, FRQSEL, SFOUT, and AUTOSEL, and dual LVPECL/LVDS/CML/CMOS programmable outputs with independent enable/bypass control via DBL2_BY.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Frequency Range	19.44–707 MHz - supports OC-48 (155.52 MHz), OC-192 (9953.28 MHz ÷ 64 = 155.52 MHz), and 10GbE reference clocks.
Output Frequency Range	19.44–1050 MHz - covers full SONET/SDH, Ethernet (156.25 MHz, 312.5 MHz), and Fibre Channel (1.0625 GHz) rates.
Jitter Generation	0.47 psRMS (50 kHz–80 MHz) - meets stringent OC-192 BER requirements and enables clean sampling in high-speed SerDes.
DSPLL Loop Bandwidth	150 kHz–1.3 MHz - digitally set via BWSEL[1:0] pins to balance jitter attenuation vs. tracking performance.
Supply Voltage	1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10% - single-rail operation simplifies power design; LVPECL outputs require ≥2.5 V nominal.
Package	36-pin QFN, 6 × 6 mm - RoHS-compliant, thermally enhanced ground pad, compatible with standard reflow profiles.
Operating Temperature	–40 °C to +85 °C - qualified for industrial-grade line card deployment in telecom infrastructure.

Pinout & Package

SI5322-C-GMR uses a 36-pin, 6 × 6 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standardized layout for signal integrity and thermal management, including dedicated VDD/GND pairs and differential I/O routing.

Pin/Terminal	Circuit Role	Design Meaning
RST	LVCMOS active-low reset	Hardware-initiated device reset; tristates outputs and triggers internal self-calibration on rising edge.
CKIN1+/CKIN1–	Differential clock input 1	Accepts 19.44–707 MHz LVPECL/LVDS/CML; supports single-ended drive with proper termination.
CKIN2+/CKIN2–	Differential clock input 2	Redundant input for automatic/manual failover; same frequency as CKIN1 required.
CKOUT1+/CKOUT1–	Differential clock output 1	Programmable format (LVPECL/LVDS/CML/CMOS); frequency matched to selected table entry.
CKOUT2+/CKOUT2–	Differential clock output 2	Independent enable/disable via DBL2_BY; supports bypass mode to route CKIN directly to output.
FRQSEL[3:0]	Three-level frequency select	4-bit encoding selects multiplication ratio from FRQTBL-defined table (e.g., 155.52 MHz → 622.08 MHz ×4).
BWSEL[1:0]	Three-level loop bandwidth select	2-bit encoding sets DSPLL closed-loop bandwidth (150 kHz, 300 kHz, 600 kHz, or 1.3 MHz) for jitter vs. tracking trade-off.
SFOUT[1:0]	Three-level signal format select	Configures common-mode voltage and swing for both outputs: LVPECL (VDD−1.3 V), LVDS (1.2 V), CML (425 mV), or CMOS.
AUTOSEL	Three-level clock selection mode	L = manual (CS_CA selects input), M = auto non-revertive, H = auto revertive - determines failover behavior during LOS.
C1B / C2B	LVCMOS loss-of-signal indicators	Active-high alarms signaling invalid input on CKIN1 or CKIN2; latch until valid signal returns.

Key Features

Feature	Design Value
Integrated DSPLL® with no external loop filter	Eliminates discrete VCXO, capacitors, and resistors - reduces BOM count and board area by >30% versus discrete PLL designs.
Dual-input redundancy with automatic switching	Supports hitless switchover between primary/backup clocks using CS_CA status feedback and configurable revertive logic.
Programmable output signal formats	Single pin-pair (SFOUT[1:0]) configures both outputs for LVPECL, LVDS, CML, or CMOS - avoids redesign when interface standards change.
On-chip voltage regulator	Enables stable 1.8 V ±5% core operation from 2.5 V or 3.3 V supply - removes need for external LDO in multi-rail systems.
Pin-programmable frequency tables	FRQTBL + FRQSEL[3:0] selects pre-validated SONET, datacom, or translation ratios - eliminates firmware configuration overhead.
Loss-of-signal detection with digital hold	Freezes DCO near last valid frequency during dual-input failure - maintains timing continuity for up to milliseconds in critical links.

Applications

SONET/SDH Line Cards	10GbE Datacom Systems
Use Scenario: Timing recovery and distribution on OC-192/STM-64 line cards requiring ultra-low jitter for FEC decoding and OTU2 framing. IC Role / Device Role / Timing Role: Precision clock multiplier generating 622.08 MHz and 1244.16 MHz outputs from 155.52 MHz reference, with DSPLL jitter cleaning. Use Value: 0.47 psRMS jitter ensures <1e−12 BER at 10.709 Gbps; integrated loop filter eliminates tuning effort and improves yield.	Use Scenario: Synchronizing XAUI interfaces and SerDes PHYs in 10GbE switches and routers with redundant clock sources. IC Role / Device Role / Timing Role: Dual-output clock generator providing 156.25 MHz and 312.5 MHz clocks with automatic failover between primary and backup oscillators. Use Value: AUTOSEL-driven switching with sub-200 ps phase step enables hitless transitions; C1B/C2B signals feed system health monitoring.
Fibre Channel Storage Networks	Optical Transport Modules
Use Scenario: Clocking 4G/8G/10GFC transceivers in storage area network (SAN) switches where deterministic latency and jitter are critical. IC Role / Device Role / Timing Role: Low-jitter frequency translator converting 140.25 MHz FC-PI-4 reference to 1062.5 MHz for 10GFC lanes. Use Value: ITU G.709 FEC ratio support (255/238) ensures compliance; LVPECL outputs drive 100 Ω transmission lines directly.	Use Scenario: Timing engine in pluggable optical modules (XFP, SFP+, QSFP) requiring compact, low-power, and pin-configurable clock synthesis. IC Role / Device Role / Timing Role: Single-supply (3.3 V) clock multiplier generating 155.52 MHz and 622.08 MHz from crystal oscillator or recovered clock. Use Value: 6 × 6 mm QFN footprint fits tight module layouts; CMOS output option supports low-power microcontroller interfaces.

SONET/SDH Line Cards

10GbE Datacom Systems

Use Scenario: Timing recovery and distribution on OC-192/STM-64 line cards requiring ultra-low jitter for FEC decoding and OTU2 framing.

IC Role / Device Role / Timing Role: Precision clock multiplier generating 622.08 MHz and 1244.16 MHz outputs from 155.52 MHz reference, with DSPLL jitter cleaning.

Use Value: 0.47 psRMS jitter ensures <1e−12 BER at 10.709 Gbps; integrated loop filter eliminates tuning effort and improves yield.

Use Scenario: Synchronizing XAUI interfaces and SerDes PHYs in 10GbE switches and routers with redundant clock sources.

IC Role / Device Role / Timing Role: Dual-output clock generator providing 156.25 MHz and 312.5 MHz clocks with automatic failover between primary and backup oscillators.

Use Value: AUTOSEL-driven switching with sub-200 ps phase step enables hitless transitions; C1B/C2B signals feed system health monitoring.

Fibre Channel Storage Networks

Optical Transport Modules

Use Scenario: Clocking 4G/8G/10GFC transceivers in storage area network (SAN) switches where deterministic latency and jitter are critical.

IC Role / Device Role / Timing Role: Low-jitter frequency translator converting 140.25 MHz FC-PI-4 reference to 1062.5 MHz for 10GFC lanes.

Use Value: ITU G.709 FEC ratio support (255/238) ensures compliance; LVPECL outputs drive 100 Ω transmission lines directly.

Use Scenario: Timing engine in pluggable optical modules (XFP, SFP+, QSFP) requiring compact, low-power, and pin-configurable clock synthesis.

IC Role / Device Role / Timing Role: Single-supply (3.3 V) clock multiplier generating 155.52 MHz and 622.08 MHz from crystal oscillator or recovered clock.

Use Value: 6 × 6 mm QFN footprint fits tight module layouts; CMOS output option supports low-power microcontroller interfaces.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock multiplier applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332-D-GM	Successor family with lower jitter (0.23 psRMS), wider output range (up to 1.4 GHz), and I²C programmability instead of pin-strapping.	Requires firmware integration; not pin-compatible; supports dynamic rate changes and spread-spectrum clocking.	Preferred for new designs needing higher performance, flexibility, or digital control - replaces SI5322-C-GMR where layout revision is acceptable.
Si5338-A-GM	Quad-output, software-programmable clock generator with identical DSPLL® core; supports fractional-N synthesis and multiple independent frequencies.	Higher channel count and configurability; larger 40-pin QFN package; requires Si5338 programming software and EEPROM.	Selected when multi-frequency generation (e.g., 125 MHz + 156.25 MHz + 312.5 MHz) or field-upgradable timing is required.

Compared with SI5322-C-GMR, Si5332-D-GM delivers 2× lower jitter and digital reconfiguration but mandates PCB redesign and firmware support, while Si5338-A-GM adds output flexibility at the cost of increased complexity and footprint - both serve distinct upgrade paths rather than drop-in replacements.

Availability

SI5322-C-GMR is available at Aetrix Electronics and suitable for SONET/SDH line cards, 10GbE datacom systems, Fibre Channel storage networks, and optical transport modules requiring stable component supply across extended product lifecycles.

Supply support for SI5322-C-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of RF and precision timing expertise.

The SI5322-C-GMR belongs to Skyworks' Any-Frequency Precision Clock family, engineered specifically for carrier-grade communication equipment demanding ultra-low jitter, dual-input redundancy, and simplified clock tree design.

FAQ

What is the primary function of the SI5322-C-GMR in a timing system?

The SI5322-C-GMR serves as a pin-programmable precision clock multiplier that accepts two redundant input clocks (19.44–707 MHz) and generates two low-jitter, frequency-multiplied outputs (19.44–1050 MHz). Its DSPLL® architecture cleans input jitter while maintaining exact frequency relationships required for SONET, Ethernet, and Fibre Channel applications - making SI5322-C-GMR ideal for line card timing where deterministic phase alignment and hitless failover are essential.

Does the SI5322-C-GMR support automatic clock switching between its two inputs?

Yes, the SI5322-C-GMR supports automatic clock switching via the AUTOSEL pin. When configured to M (auto non-revertive) or H (auto revertive), it monitors both CKIN1 and CKIN2 for loss-of-signal using internal comparators. Upon detecting LOS on the active input, it switches to the healthy input and asserts the corresponding C1B or C2B alarm. The CS_CA pin then indicates the currently active source - a key capability built into SI5322-C-GMR for telecom-grade reliability.

Can the SI5322-C-GMR generate different output frequencies on CKOUT1 and CKOUT2?

No, the SI5322-C-GMR generates identical frequencies on both CKOUT1 and CKOUT2. The device uses a single DSPLL® core with one multiplication ratio selected via FRQSEL[3:0] and FRQTBL; both outputs are derived from the same DCO. While CKOUT2 can be disabled or placed in bypass mode (routing CKIN directly), its frequency cannot differ from CKOUT1 - this fixed dual-output architecture is a defining characteristic of SI5322-C-GMR.

What supply voltage options does the SI5322-C-GMR support, and which outputs require higher voltage?

The SI5322-C-GMR operates from a single 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10% supply. LVPECL output format requires a nominal supply voltage greater than 2.5 V (i.e., 2.5 V or 3.3 V), while LVDS, CML, and CMOS formats function across all three supply rails. This constraint is explicitly specified in the datasheet and applies to both CKOUT1 and CKOUT2 when configured for LVPECL - a critical design consideration for SI5322-C-GMR power planning.

Is the SI5322-C-GMR recommended for new designs, and what is the official alternative?

No, Skyworks explicitly states "Not recommended for new designs" for the SI5322-C-GMR, directing users to the Si533x family. The Si5332-D-GM is the designated successor, offering lower jitter (0.23 psRMS), higher maximum output frequency (1.4 GHz), I²C programmability, and enhanced features like spread-spectrum clocking. While SI5322-C-GMR remains available for legacy support and existing production, new projects should evaluate Si5332-D-GM as the approved replacement path.

SI5322-C-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL®

Package/Case:: 36-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Multiplier

PLL:: Yes

Input:: LVCMOS

Output:: CML, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 2:2

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 1.05GHz

Divider/Multiplier:: No/Yes

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 36-QFN (6x6)

SI5322-C-GMR FAQ

1.How can I place an order for SI5322-C-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5322-C-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5322-C-GMR reliable?

The price and inventory of SI5322-C-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5322-C-GMR is usually 5 days.

3.What payment methods are accepted for SI5322-C-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5322-C-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5322-C-GMR?

SI5322-C-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5322-C-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5322-C-GMR?

For technical support, including SI5322-C-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5322-C-GMR requirements.

6.How does Aetrix verify that SI5322-C-GMR is sourced from the original manufacturer or authorized distributors?

All SI5322-C-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5322-C-GMR meets industry standards.

7.What is the process for return or replacement of SI5322-C-GMR?

All SI5322-C-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5322-C-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5322-C-GMR part is unused and in its original packaging.

Return procedure for SI5322-C-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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