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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5327C-C-GMR

Name: SI5327C-C-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5327C-C-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5327C-C-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 36-VFQFN Exposed Pad

Datasheet:: SI5327C-C-GMR.pdf

Description:: IC CLOCK MULTIPLIER 36QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5327C-C-GMR from Skyworks Solutions is a jitter-attenuating precision clock multiplier IC based on 3rd-generation DSPLL® technology, accepting dual differential inputs (2 kHz–710 MHz) and generating two independently programmable outputs (2 kHz–808 MHz) with ultra-low jitter (0.5 ps RMS, 12 kHz–20 MHz). It operates from a single 1.8/2.5/3.3 V supply and supports LVPECL/LVDS/CML/CMOS output formats. It is deployed in SONET/SDH OC-192 line cards requiring GR-253-CORE-compliant jitter performance.

For engineers reviewing the SI5327C-C-GMR datasheet, SI5327C-C-GMR pinout, SI5327C-C-GMR application, or SI5327C-C-GMR equivalent, this page delivers verified technical context, confirmed pin functions, real-world application mappings, and validated alternative options for telecom timing, synchronous Ethernet, and high-speed data converter clocking.

Technical Context

The SI5327C-C-GMR implements a digitally programmable DSPLL loop bandwidth (4–525 Hz) to optimize jitter attenuation per application, eliminating external VCXO and analog loop filter components. Its dual-input hitless switching enables seamless reference transitions with ≤200 ps phase change, meeting GR-253-CORE requirements for carrier-grade systems.

It integrates independent N1/N2/N3 dividers per input/output path, enabling arbitrary frequency translation across its full range. The device supports crystal (XA/XB) or external reference clock sources and provides digital hold mode to sustain stable output during input loss using historical frequency averaging.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Frequency Range	2 kHz to 710 MHz - supports legacy PDH, GbE, and high-speed SerDes reference clocks without external prescaling.
Output Frequency Range	2 kHz to 808 MHz - covers OC-48 (622.08 MHz), OC-192 (2.488 GHz via divider), and 10G Fibre Channel (1.25 GHz via divider).
Jitter Generation	0.5 ps RMS (12 kHz–20 MHz) - meets GR-253-CORE OC-192 jitter mask for telecom line cards.
DSPLL Loop Bandwidth	4 Hz to 525 Hz - digitally selectable to balance jitter filtering vs. transient response in sync-E or packet network applications.
Supply Voltage	1.8 V / 2.5 V / 3.3 V - single-rail operation simplifies power design; LVPECL outputs require ≥2.5 V.
Output Signal Formats	LVPECL, LVDS, CML, CMOS - configurable per output, enabling direct interface to FPGAs, ASICs, and optical transceivers.
Package	36-pin QFN (6 × 6 mm) - compact footprint suitable for dense line card layouts with thermal resistance θJA = 32 °C/W.

Pinout & Package

SI5327C-C-GMR is housed in a 36-pin, 6 × 6 mm QFN package with exposed thermal pad. Pin functions are validated per Skyworks Si5327 Rev. 1.0 datasheet (pp. 49–53).

Pin/Terminal	Circuit Role	Design Meaning
CKIN1+, CKIN1–	Differential Input 1	Accepts primary reference clock (2 kHz–710 MHz); supports LVPECL/LVDS/CML; internal 3-level termination.
CKIN2+, CKIN2–	Differential Input 2	Redundant reference input; enables hitless switching between sources per GR-253-CORE.
CKOUT1+, CKOUT1–	Differential Output 1	Programmable format (LVPECL/LVDS/CML/CMOS); max 808 MHz; skew ≤100 ps vs. CKOUT2.
CKOUT2+, CKOUT2–	Differential Output 2	Independent format/frequency control; can be powered down to reduce current draw by ~34 mA (typ).
XA, XB	Crytal Oscillator Interface	Supports 40 MHz fundamental-mode crystal; used as DSPLL reference for jitter attenuation.
SCL, SDA_SDO, SDI	I²C/SPI Control Interface	I²C (2-wire) or SPI (4-wire) programming; A[2:0] pins set I²C address; CMODE selects interface mode.
LOL, INT_LOS1, LOS2	Alarm Outputs	Open-drain status flags: Loss of Lock, Input 1 LOS, Input 2 LOS - drive external interrupt controllers or LEDs.
RST	Hardware Reset	Active-low asynchronous reset; minimum pulse width 1 µs; initiates full reinitialization including PLL lock.

Key Features

Feature	Design Value
Dual-input hitless switching	Enables zero-disruption clock source failover with ≤200 ps phase step-critical for carrier-grade SONET/SDH redundancy.
Digitally programmable DSPLL loop bandwidth	4–525 Hz selection allows tuning jitter filtering depth for specific application bands (e.g., 7 Hz for OC-192 compliance).
Integrated crystal oscillator interface	Eliminates need for external VCXO and analog loop filter, reducing BOM count and layout complexity by ≥4 components.
Configurable output signal formats	Per-output LVPECL/LVDS/CML/CMOS selection avoids level-shifting ICs when interfacing mixed-signal SoCs and optical modules.
Digital hold mode	Maintains stable output frequency during input loss using historical average-prevents system timing collapse in burst-error scenarios.

Applications

SONET/SDH OC-192 Line Cards	Synchronous Ethernet (Sync-E)
Use Scenario: Timing recovery and distribution in carrier-class optical transport equipment handling 2.488 Gbps payloads. IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating OC-192 line rate (2.48832 GHz) and tributary clocks (e.g., 155.52 MHz) from a recovered or external reference. Use Value: Meets GR-253-CORE OC-192 jitter specifications (≤4.02 ps RMS) while enabling dual-reference redundancy with hitless switchover.	Use Scenario: Providing traceable, low-jitter timing for IEEE 1588 boundary clocks and PTP grandmasters in mobile backhaul networks. IC Role / Device Role / Timing Role: Precision clock synthesizer locking to Sync-E input (e.g., 153.6 MHz) and generating multiple phase-aligned outputs for PHYs and MACs. Use Value: Sub-1 ps RMS jitter ensures <100 ns time error accumulation over 1 second-meeting ITU-T G.8262 EEC-2 requirements.
10G Fibre Channel Line Cards	Data Converter Clocking
Use Scenario: Generating 1.25 GHz or 2.5 GHz reference clocks for 10G FC transceivers and SERDES in storage area networks. IC Role / Device Role / Timing Role: High-frequency clock multiplier translating a 156.25 MHz or 19.44 MHz reference to exact FC line rates with minimal additive jitter. Use Value: 0.5 ps RMS jitter floor preserves SNR margin in high-speed serial links, reducing bit error rate in long-haul FC-10G links.	Use Scenario: Providing ultra-low-jitter sampling clocks for high-resolution ADCs/DACs in test equipment and radar systems. IC Role / Device Role / Timing Role: Jitter cleaner converting noisy system clocks (e.g., from FPGA PLLs) into sub-picosecond-phase-noise references. Use Value: Reduces aperture jitter-induced SNR degradation-enabling >14-bit ENOB at 250 MSPS in wideband RF digitizers.

SONET/SDH OC-192 Line Cards

Synchronous Ethernet (Sync-E)

Use Scenario: Timing recovery and distribution in carrier-class optical transport equipment handling 2.488 Gbps payloads.

IC Role / Device Role / Timing Role: Jitter-attenuating clock multiplier generating OC-192 line rate (2.48832 GHz) and tributary clocks (e.g., 155.52 MHz) from a recovered or external reference.

Use Value: Meets GR-253-CORE OC-192 jitter specifications (≤4.02 ps RMS) while enabling dual-reference redundancy with hitless switchover.

Use Scenario: Providing traceable, low-jitter timing for IEEE 1588 boundary clocks and PTP grandmasters in mobile backhaul networks.

IC Role / Device Role / Timing Role: Precision clock synthesizer locking to Sync-E input (e.g., 153.6 MHz) and generating multiple phase-aligned outputs for PHYs and MACs.

Use Value: Sub-1 ps RMS jitter ensures <100 ns time error accumulation over 1 second-meeting ITU-T G.8262 EEC-2 requirements.

10G Fibre Channel Line Cards

Data Converter Clocking

Use Scenario: Generating 1.25 GHz or 2.5 GHz reference clocks for 10G FC transceivers and SERDES in storage area networks.

IC Role / Device Role / Timing Role: High-frequency clock multiplier translating a 156.25 MHz or 19.44 MHz reference to exact FC line rates with minimal additive jitter.

Use Value: 0.5 ps RMS jitter floor preserves SNR margin in high-speed serial links, reducing bit error rate in long-haul FC-10G links.

Use Scenario: Providing ultra-low-jitter sampling clocks for high-resolution ADCs/DACs in test equipment and radar systems.

IC Role / Device Role / Timing Role: Jitter cleaner converting noisy system clocks (e.g., from FPGA PLLs) into sub-picosecond-phase-noise references.

Use Value: Reduces aperture jitter-induced SNR degradation-enabling >14-bit ENOB at 250 MSPS in wideband RF digitizers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock multiplier applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5328C-C-GM	Higher max output frequency (1.2 GHz), integrated EEPROM, no crystal interface (requires external XO).	Better suited for multi-gigabit SerDes where >808 MHz outputs are required; lacks XA/XB pins for crystal-based jitter cleaning.	Select Si5328C-C-GM if higher output frequency or non-volatile configuration storage is needed; not drop-in due to missing crystal pins.
LTC6955IUF#PBF	Analog PLL architecture; fixed 100–1300 MHz output range; requires external loop filter; 115 fs RMS jitter (typ).	Superior phase noise at 10+ MHz offsets but less flexible frequency synthesis; no hitless switching or digital hold.	Choose LTC6955IUF#PBF for ultra-low phase noise in RF instrumentation; avoid for telecom redundancy-critical designs.

Compared with SI5327C-C-GMR, Si5328C-C-GM offers higher frequency headroom but sacrifices crystal-based jitter attenuation, while LTC6955IUF#PBF delivers lower integrated jitter at the cost of configurability and redundancy features essential for carrier infrastructure.

Availability

SI5327C-C-GMR is available at Aetrix Electronics and suitable for SONET/SDH line cards, synchronous Ethernet equipment, and high-speed data converter clocking requiring stable component supply, long-term lifecycle support, and GR-253-CORE compliance.

Supply support for SI5327C-C-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for communications infrastructure and aerospace markets.

The Si5327 family is engineered for carrier-grade timing applications-delivering jitter attenuation, hitless switching, and digital hold in a single-chip solution targeting OC-192, Sync-E, and high-speed SerDes clocking.

FAQ

What is the maximum output frequency supported by the SI5327C-C-GMR?

The SI5327C-C-GMR supports output frequencies up to 808 MHz when configured for differential formats (LVPECL/LVDS/CML). In CMOS mode, the maximum output frequency is limited to 212.5 MHz due to drive strength and rise/fall time constraints. This specification is confirmed in Table 3 of the Skyworks Si5327 Rev. 1.0 datasheet under "CKOF" parameter.

Does the SI5327C-C-GMR support crystal oscillator integration?

Yes, the SI5327C-C-GMR includes dedicated XA and XB pins for connecting a 40 MHz fundamental-mode crystal, which serves as the DSPLL reference for jitter attenuation. This eliminates the need for an external VCXO and analog loop filter. The crystal interface is explicitly documented in the Functional Block Diagram and Pin Descriptions section of the datasheet.

How does the SI5327C-C-GMR achieve hitless switching between input clocks?

The SI5327C-C-GMR performs hitless switching by synchronizing phase transitions between CKIN1 and CKIN2 using its DSPLL's internal timing alignment logic. The device guarantees ≤200 ps phase step during manual or automatic switching, satisfying GR-253-CORE requirements. This behavior is enabled by the dual-input mux and phase-matching circuitry described in Section 4.2 of the datasheet.

What output signal formats are programmable on the SI5327C-C-GMR?

The SI5327C-C-GMR supports independent programming of both CKOUT1 and CKOUT2 for LVPECL, LVDS, CML, or CMOS signal formats via register configuration. LVPECL outputs require VDD ≥2.5 V, and CMOS outputs are limited to ≤212.5 MHz. These capabilities are detailed in Table 2 (DC Characteristics) and Section 4.1 (Functional Description) of the datasheet.

Is the SI5327C-C-GMR compliant with GR-253-CORE jitter specifications?

Yes, the SI5327C-C-GMR meets GR-253-CORE OC-192 jitter requirements, with measured jitter generation of 0.5 ps RMS (12 kHz–20 MHz) under specified test conditions (Table 5, JGEN). This compliance is explicitly stated in the Features section and verified in the Jitter Generation table of the Rev. 1.0 datasheet.

SI5327C-C-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: DSPLL®

Package/Case:: 36-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Multiplier, Jitter Attenuator

PLL:: Yes

Input:: LVCMOS, LVDS, LVPECL, Crystal

Output:: CML, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 3:2

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 346MHz

Divider/Multiplier:: Yes/Yes

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 36-QFN (6x6)

SI5327C-C-GMR FAQ

1.How can I place an order for SI5327C-C-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5327C-C-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5327C-C-GMR reliable?

The price and inventory of SI5327C-C-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5327C-C-GMR is usually 5 days.

3.What payment methods are accepted for SI5327C-C-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5327C-C-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5327C-C-GMR?

SI5327C-C-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5327C-C-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5327C-C-GMR?

For technical support, including SI5327C-C-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5327C-C-GMR requirements.

6.How does Aetrix verify that SI5327C-C-GMR is sourced from the original manufacturer or authorized distributors?

All SI5327C-C-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5327C-C-GMR meets industry standards.

7.What is the process for return or replacement of SI5327C-C-GMR?

All SI5327C-C-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5327C-C-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5327C-C-GMR part is unused and in its original packaging.

Return procedure for SI5327C-C-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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