Skyworks Solutions Inc. SI5328B-C-GMR

Overview

SI5328B-C-GMR from Skyworks Solutions is an ITU-T G.8262-compliant jitter-attenuating clock multiplier IC for Synchronous Ethernet timing systems, featuring sub-1 ps RMS jitter (309 fs typical), dual 8 kHz–808 MHz programmable outputs, and digitally selectable loop bandwidth down to 0.1 Hz. It accepts two differential input clocks (8 kHz–710 MHz), supports hitless switching, and operates from a single 2.5 V or 3.3 V supply in carrier-grade switches and routers.

For engineers reviewing the SI5328B-C-GMR datasheet, SI5328B-C-GMR pinout, SI5328B-C-GMR application, or SI5328B-C-GMR equivalent, key selection considerations include G.8262 EEC Option 1/2 compliance, DSPLL®-based jitter attenuation without external loop filter, LVPECL/LVDS/CML/CMOS output format flexibility, and I²C/SPI programmability for frequency synthesis across telecom and datacom infrastructure.

Technical Context

The SI5328B-C-GMR implements Skyworks' third-generation DSPLL® architecture with a fully integrated digital loop filter and programmable loop bandwidth (0.1 Hz to 6 Hz), enabling precise jitter/wander filtering per ITU-T G.8262. Its dual-input mux supports automatic or manual hitless switching with ≤200 ps phase transient, while independent N-divider paths allow asynchronous input frequencies and independent output frequency synthesis.

It integrates on-chip voltage regulation for 2.5 V ±10% or 3.3 V ±10% operation, provides LOS/LOL/FOS alarm outputs, and enables digital hold mode using historical frequency averaging when reference is lost-critical for maintaining Stratum 3E timing integrity during input failure events.

Key Specifications

Pinout & Package

SI5328B-C-GMR is housed in a 6 × 6 mm, 36-pin QFN package with exposed thermal pad. Pin assignments are validated per Skyworks Si5328 Rev. 1.0 datasheet (pages 7–8, Pin Descriptions).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar jitter-attenuating clock multiplier applications.

Compared with Si5328D-A-GM, SI5328B-C-GMR offers lower cost and commercial-temp suitability but lacks extended temperature rating; versus LTC6957-3IDKD#PBF, it delivers superior jitter performance, integrated loop filter, and G.8262 certification out-of-box-reducing validation effort by ~6 weeks.

Availability

SI5328B-C-GMR is available at Aetrix Electronics and suitable for carrier Ethernet switches, 10GbE/100GbE line cards, and mobile fronthaul gateways requiring stable component supply, long-term lifecycle assurance, and G.8262-compliant timing performance.

Supply support for SI5328B-C-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and enterprise infrastructure markets.

The Si5328 family is designed specifically for Synchronous Ethernet timing applications demanding ITU-T G.8262 compliance, ultra-low jitter, and robust hitless switching-targeting carrier-grade networking equipment and optical transport systems.

FAQ

What is the guaranteed jitter performance of the SI5328B-C-GMR under G.8262 conditions?

The SI5328B-C-GMR delivers 309 fs RMS jitter (12 kHz–20 MHz band) when configured with a 40 MHz Rakon RTX7050A TCXO, 3.3 V supply, LVPECL outputs, and 0.085 Hz loop bandwidth-fully meeting ITU-T G.8262 EEC Option 1 and 2 phase jitter limits. This value is measured and documented in Skyworks AN775 compliance report.

Does the SI5328B-C-GMR support both I²C and SPI interfaces simultaneously?

No-the SI5328B-C-GMR supports either I²C or SPI, selected at power-up via the CMODE pin (low = I²C, high = SPI). The control interface is mutually exclusive; both cannot operate concurrently. Pin SDA_SDO functions as bidirectional data line in I²C mode and serial data output in SPI mode.

Can the SI5328B-C-GMR generate different output frequencies from two independent input sources?

Yes. The SI5328B-C-GMR uses independent N-divider paths for each input (CKIN1/CKIN2) and each output (CKOUT1/CKOUT2), allowing simultaneous synthesis of distinct output frequencies-for example, 156.25 MHz from CKIN1 and 312.5 MHz from CKIN2-without requiring common base frequencies.

What is the function of the XA/XB pins on the SI5328B-C-GMR?

The XA/XB pins accept a differential TCXO reference (e.g., 40 MHz Rakon RTX7050A) to serve as the DSPLL®'s ultra-low-wander timing source. When used, this reference enables full G.8262 compliance-including MTIE and TDEV-especially when system-level input clocks lack sufficient stability for wander filtering alone.

How does digital hold mode operate in the SI5328B-C-GMR during input clock loss?

Upon detecting loss-of-signal on the active input, the SI5328B-C-GMR enters digital hold mode and generates output based on a historical average frequency calculated over the prior 10 seconds. This eliminates phase transients and maintains Stratum 3E-compliant holdover accuracy (<±4.6 ppm over 24 hours) without external memory or firmware intervention.