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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5332AC09097-GM2R

Name: SI5332AC09097-GM2R
Brand: Skyworks Solutions Inc.
SKU: SI5332AC09097-GM2R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5332AC09097-GM2R

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5332AC09097-GM2R.pdf

Description:: IC CLOCK GENERATOR QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5332AC09097-GM2R from Silicon Labs is an 8-output, factory-programmed, low-jitter clock generator using MultiSynth™ fractional synthesis. It delivers up to 333.33 MHz differential outputs with 190 fs RMS phase jitter (external crystal), supports LVDS/LVPECL/HCSL/LVCMOS per-output format selection, and operates across –40 to +85 °C for Ethernet switch timing and server clock tree consolidation.

For engineers reviewing the SI5332AC09097-GM2R datasheet, SI5332AC09097-GM2R pinout, SI5332AC09097-GM2R application, or SI5332AC09097-GM2R equivalent, key selection considerations include its 40-pin QFN package, 8-differential-output capability, embedded configuration for PCIe Gen4-compliant clocks, I²C programmability, and mixed-supply bank architecture enabling independent 1.8/2.5/3.3 V output voltage domains.

Technical Context

The SI5332AC09097-GM2R implements a two-stage synthesis architecture: a wideband PLL locks to a 16–50 MHz external crystal (XA/XB), then feeds up to three independent MultiSynth fractional dividers and five integer dividers. Its cross-point mux routes any synthesized or divided frequency to any of eight differential outputs.

Each output bank has dedicated VDDO pins supporting 1.8 V, 2.5 V, or 3.3 V supply voltages; differential outputs are configurable for LVDS, LVPECL, HCSL, or LVCMOS with programmable skew (±245 ps in 35 ps steps) and synchronous enable/disable. The device stores one factory-programmed configuration in NVM and supports in-system reprogramming via I²C.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 differential clock outputs (Si5332-GM2 variant)
Jitter (RMS)	190 fs - meets PCIe Gen4 SRIS requirements for high-speed serial links
Max output frequency	333.33 MHz differential - supports DDR4/5 memory clocks and 100G Ethernet line rates
Input reference	16–50 MHz external crystal - enables stable free-run operation without external clock source
Output formats	Per-output LVDS / LVPECL / HCSL / LVCMOS - eliminates need for external level translators
Supply flexibility	Independent VDDO banks at 1.8/2.5/3.3 V - allows mixed-voltage SoC interfacing on single device
Package	40-pin QFN (6 × 6 mm) - standard surface-mount footprint compatible with automated assembly

Pinout & Package

SI5332AC09097-GM2R uses a 40-pin QFN (6 × 6 mm) package with exposed thermal pad. Pin functions follow the Si5332-GM2 40-QFN layout: six VDDO pins power four dedicated-output channels and two output banks (Bank A/B), seven universal hardware input pins support OE, spread-spectrum enable, or input selection, and XA/XB connect to external crystal.

Pin/Terminal	Circuit Role	Design Meaning
XA / XB	Crystal oscillator input	Connects directly to 16–50 MHz fundamental-mode crystal; internal load capacitance configurable via register
VDDO0–VDDO5	Output supply rails	Power banks: VDDO0/VDDO1 for Bank A (OUT0/OUT1), VDDO2/VDDO3 for Bank B (OUT2/OUT3), VDDO4/VDDO5 for dedicated OUT6/OUT7
OUT0–OUT7	Differential clock outputs	Each pair (e.g., OUT0/OUT0b) configurable as LVDS/LVPECL/HCSL/LVCMOS; skew adjustable ±245 ps
SCLK / SDATA	I²C serial interface	Supports in-system programming and runtime configuration updates without power cycle
IN1–IN7	Universal hardware inputs	Configurable in ClockBuilder Pro as OE, CLKIN_SEL, SS_EN, or I²C address select - no external logic required

Key Features

Feature	Design Value
MultiSynth™ fractional synthesis	Enables any-frequency generation up to 250 MHz on any output with zero ppm error - replaces multiple fixed-frequency oscillators
Cross-point mux architecture	Routes any MultiSynth or integer divider output to any of 8 differential outputs - maximizes routing flexibility for complex clock trees
Per-output signal format control	LVDS/LVPECL/HCSL/LVCMOS selectable per channel - eliminates discrete level-shifting components in multi-protocol systems
Independent output supply banks	Four VDDO domains allow simultaneous 1.8 V, 2.5 V, and 3.3 V outputs - supports heterogeneous ASIC/FPGA interfaces
Factory-programmed NVM config	SI5332AC09097-GM2R powers up with preloaded ClockBuilder Pro configuration - no host initialization required

Applications

Ethernet Switch Timing	Server Memory Subsystem
Use Scenario: 100G/400G Ethernet switch ASIC requiring synchronized 156.25 MHz, 312.5 MHz, and 625 MHz reference clocks with sub-200 fs jitter. IC Role / Device Role / Timing Role: Primary clock generator providing all line-rate and core-clock references from single device. Use Value: Eliminates 4+ discrete oscillators and fanout buffers while maintaining PCIe Gen4-compliant jitter for SerDes lock.	Use Scenario: Dual-socket server motherboard needing DDR5 memory clocks (up to 6400 MT/s), CPU reference (100 MHz), and BMC timing (32.768 kHz). IC Role / Device Role / Timing Role: Consolidated clock source generating integer and non-integer frequencies across mixed-voltage domains. Use Value: Reduces BOM count by 70% vs. discrete clock solution and enables per-bank voltage scaling for power optimization.
Broadcast Video Synchronization	Industrial Embedded Computing
Use Scenario: 4K/8K video encoder board requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz SMPTE ST 2082-1 compliant clocks. IC Role / Device Role / Timing Role: Jitter-clean master clock generator with programmable spread spectrum for EMI reduction in dense PCB layouts. Use Value: Meets ±20 ppm frequency accuracy and <190 fs jitter for broadcast-grade video timing without external filtering.	Use Scenario: Ruggedized edge AI gateway needing reliable 25 MHz, 125 MHz, and 200 MHz clocks for FPGA, Ethernet PHY, and real-time processor under –40 to +85 °C. IC Role / Device Role / Timing Role: Industrial-grade clock generator with extended temperature operation and robust crystal start-up. Use Value: Guarantees deterministic clock behavior across thermal cycling and vibration - no configuration drift or startup failure.

Ethernet Switch Timing

Server Memory Subsystem

Use Scenario: 100G/400G Ethernet switch ASIC requiring synchronized 156.25 MHz, 312.5 MHz, and 625 MHz reference clocks with sub-200 fs jitter.

IC Role / Device Role / Timing Role: Primary clock generator providing all line-rate and core-clock references from single device.

Use Value: Eliminates 4+ discrete oscillators and fanout buffers while maintaining PCIe Gen4-compliant jitter for SerDes lock.

Use Scenario: Dual-socket server motherboard needing DDR5 memory clocks (up to 6400 MT/s), CPU reference (100 MHz), and BMC timing (32.768 kHz).

IC Role / Device Role / Timing Role: Consolidated clock source generating integer and non-integer frequencies across mixed-voltage domains.

Use Value: Reduces BOM count by 70% vs. discrete clock solution and enables per-bank voltage scaling for power optimization.

Broadcast Video Synchronization

Industrial Embedded Computing

Use Scenario: 4K/8K video encoder board requiring genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz SMPTE ST 2082-1 compliant clocks.

IC Role / Device Role / Timing Role: Jitter-clean master clock generator with programmable spread spectrum for EMI reduction in dense PCB layouts.

Use Value: Meets ±20 ppm frequency accuracy and <190 fs jitter for broadcast-grade video timing without external filtering.

Use Scenario: Ruggedized edge AI gateway needing reliable 25 MHz, 125 MHz, and 200 MHz clocks for FPGA, Ethernet PHY, and real-time processor under –40 to +85 °C.

IC Role / Device Role / Timing Role: Industrial-grade clock generator with extended temperature operation and robust crystal start-up.

Use Value: Guarantees deterministic clock behavior across thermal cycling and vibration - no configuration drift or startup failure.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SI5332BC09097-GM2R	Same 40-pin QFN, 8-output, but Si5332B grade limits max output to 200 MHz (vs. 333.33 MHz)	Suitable for 10G/25G Ethernet where 200 MHz suffices; not viable for 100G+ line rates or DDR5	Select when cost sensitivity outweighs need for >200 MHz outputs and PCIe Gen4 compliance is not required
SI5332AC09097-GM3R	Same Si5332A functionality but in 48-pin QFN with 12 outputs and four VDDO banks (vs. 8 outputs, two banks)	Required for designs needing >8 clocks (e.g., multi-ASIC baseband units); larger footprint and higher pin count	Choose when expanding clock count beyond 8 outputs while retaining identical jitter, frequency, and feature set

Compared with SI5332BC09097-GM2R, the SI5332AC09097-GM2R enables higher-speed serial interfaces; compared with SI5332AC09097-GM3R, it reduces PCB area and component count where 8 outputs are sufficient - optimizing cost and layout density without sacrificing performance.

Availability

SI5332AC09097-GM2R is available at Aetrix Electronics and suitable for Ethernet switches, server memory subsystems, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and factory-programmed reliability.

Supply support for SI5332AC09097-GM2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with over two decades of leadership in precision clock technology and low-power RF design.

The Si5332 family was engineered to replace multiple discrete clock sources in high-performance computing and communications infrastructure, delivering flexible, low-jitter, software-configurable timing in compact QFN packages - specifically targeting datacenter, telecom, and broadcast applications.

FAQ

What is the maximum differential output frequency supported by the SI5332AC09097-GM2R?

The SI5332AC09097-GM2R supports differential output frequencies up to 333.33 MHz. This capability is specified for the Si5332A grade and enables direct generation of DDR5 memory clocks, 100G Ethernet line-rate clocks, and PCIe Gen4 reference frequencies without external multiplication. The limit is enforced by the device's MultiSynth architecture and validated in the Electrical Specifications section of the official datasheet.

Does the SI5332AC09097-GM2R include an embedded crystal?

No, the SI5332AC09097-GM2R does not include an embedded crystal. It belongs to the Si5332A series, which requires an external 16–50 MHz fundamental-mode crystal connected to the XA/XB pins. Embedded crystal variants (e.g., Si5332E/F/G/H) use a different ordering suffix and are not applicable to this part number.

How many independent output voltage domains does the SI5332AC09097-GM2R support?

The SI5332AC09097-GM2R supports six independent VDDO pins (VDDO0–VDDO5), grouped into two dedicated-output channels and two banks (Bank A and Bank B). Each VDDO can be set to 1.8 V, 2.5 V, or 3.3 V, allowing mixed-supply operation - for example, driving 1.8 V FPGA transceivers and 3.3 V legacy PHYs simultaneously from the same SI5332AC09097-GM2R device.

Can the SI5332AC09097-GM2R be reprogrammed after deployment?

Yes, the SI5332AC09097-GM2R supports full in-system programming via its I²C interface (SCLK/SDATA pins). While it ships with a factory-programmed configuration stored in NVM, registers can be modified dynamically during operation - enabling runtime frequency changes, output enable/disable, or spread spectrum activation without power cycling the SI5332AC09097-GM2R.

Is the SI5332AC09097-GM2R compliant with PCIe Gen4 timing requirements?

Yes, the SI5332AC09097-GM2R is explicitly designed to meet PCIe Gen4 SRIS (Scalable Reliable Interconnect Specification) requirements, with 190 fs RMS phase jitter measured at 12 kHz–20 MHz offset. This performance is verified using a 16–50 MHz external crystal and applies to all output frequencies within its specification range - confirming suitability for PCIe Gen4 root complex and endpoint timing in servers and accelerators.

SI5332AC09097-GM2R Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5332AC09097-GM2R FAQ

1.How can I place an order for SI5332AC09097-GM2R through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5332AC09097-GM2R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5332AC09097-GM2R reliable?

The price and inventory of SI5332AC09097-GM2R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332AC09097-GM2R is usually 5 days.

3.What payment methods are accepted for SI5332AC09097-GM2R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332AC09097-GM2R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5332AC09097-GM2R?

SI5332AC09097-GM2R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5332AC09097-GM2R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5332AC09097-GM2R?

For technical support, including SI5332AC09097-GM2R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332AC09097-GM2R requirements.

6.How does Aetrix verify that SI5332AC09097-GM2R is sourced from the original manufacturer or authorized distributors?

All SI5332AC09097-GM2R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332AC09097-GM2R meets industry standards.

7.What is the process for return or replacement of SI5332AC09097-GM2R?

All SI5332AC09097-GM2R units undergo pre-shipment inspection (PSI). If there is an issue with SI5332AC09097-GM2R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5332AC09097-GM2R part is unused and in its original packaging.

Return procedure for SI5332AC09097-GM2R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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