Skyworks Solutions Inc. SI5332AC09115-GM1

Overview

SI5332AC09115-GM1 from Silicon Labs is a 6-output, 32-pin QFN programmable clock generator with MultiSynth™ fractional synthesis, delivering 190 fs RMS phase jitter (external crystal), 5–333.33 MHz differential output frequency range, and support for LVDS/LVPECL/HCSL/LVCMOS signal formats per output - deployed in Ethernet switches and server timing subsystems.

For engineers reviewing the SI5332AC09115-GM1 datasheet, SI5332AC09115-GM1 pinout, SI5332AC09115-GM1 application, or SI5332AC09115-GM1 equivalent, key selection considerations include its 6-differential-output architecture, external 16–50 MHz crystal input capability, independent VDDO per output bank, I²C programmability, and PCIe Gen1–4/SRIS compliance.

Technical Context

The SI5332AC09115-GM1 implements a two-stage synthesis architecture: a wideband PLL locks to an external crystal (16–50 MHz) or differential clock input, then feeds up to three independent MultiSynth fractional dividers and five integer dividers. Its cross-point mux routes any synthesized or divided frequency to any of six differential outputs.

Each output supports user-configurable format (LVDS, LVPECL, HCSL, LVCMOS), skew adjustment (±245 ps in 35 ps steps), synchronous enable/disable, and independent VDDO supply (1.5/1.8/2.5/3.3 V), enabling mixed-voltage clock distribution in multi-rail systems without level-shifting.

Key Specifications

Pinout & Package

SI5332AC09115-GM1 uses a 32-pin QFN package (5 mm × 5 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per the Si5332A/B/C/D 32-QFN pinout (Section 6.3, Rev. 1.1 datasheet), supporting six differential outputs (OUT0–OUT5 with complementary b-pins), seven universal hardware inputs (configurable as OE, CLKIN_SEL, spread-spectrum enable, etc.), and dedicated power/ground pins.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable clock generator applications.

Compared with Si5332BC09115-GM1 and Si5338AC09115-GM1, the SI5332AC09115-GM1 uniquely delivers full 333.33 MHz bandwidth with fractional synthesis, PCIe Gen4 SRIS compliance, and 6-output flexibility - making it the only option among the three for high-speed serial link timing in next-gen infrastructure.

Availability

SI5332AC09115-GM1 is available at Aetrix Electronics and suitable for Ethernet switches, server timing subsystems, and broadcast video equipment requiring stable component supply, long-term lifecycle assurance, and factory-programmed configuration traceability.

Supply support for SI5332AC09115-GM1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with leadership in low-jitter clock technology and configurable mixed-signal ICs.

The Si5332 family was designed to replace multiple discrete clock sources in high-performance computing and communications infrastructure - delivering single-chip programmability, ultra-low jitter, and multi-voltage output flexibility.

FAQ

What is the maximum differential output frequency supported by the SI5332AC09115-GM1?

The SI5332AC09115-GM1 supports differential output frequencies from 5 MHz to 333.33 MHz. This upper limit applies to all six differential outputs and is achievable using MultiSynth fractional synthesis with zero ppm error - critical for PCIe Gen4 (100 MHz REFCLK with tight jitter margin) and 100G Ethernet applications. The 333.33 MHz capability distinguishes it from the Si5332B variant (200 MHz max).

Does the SI5332AC09115-GM1 include an embedded crystal?

No, the SI5332AC09115-GM1 does not include an embedded crystal. It belongs to the Si5332A series, which requires an external 16–50 MHz fundamental-mode crystal connected to the XA/XB pins. Embedded crystal variants (e.g., Si5332E/F/G/H) are separate part numbers; this device relies on external crystal or differential clock inputs for reference.

How many independent voltage domains does the SI5332AC09115-GM1 support for its outputs?

The SI5332AC09115-GM1 supports six independent VDDO supply pins - one per differential output pair (VDDO0 through VDDO5). Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V for LVCMOS, or 1.8 V, 2.5 V, or 3.3 V for differential formats. This enables true mixed-supply clock distribution without external level shifters or LDOs.

Can the SI5332AC09115-GM1 generate spread spectrum clocking?

Yes, the SI5332AC09115-GM1 supports both center-spread and down-spread spectrum modulation from –0.1% to –2.5% in 0.01% steps at 30–33 kHz. Spread spectrum can be enabled via I²C register write or by assigning a universal hardware input pin (e.g., IN1) as spread-enable in ClockBuilder Pro - reducing system EMI without affecting timing accuracy.

Is the SI5332AC09115-GM1 PCIe Gen4-compliant?

Yes, the SI5332AC09115-GM1 is explicitly stated as PCIe Gen1/2/3/4 and SRIS compliant in the official datasheet. Its 190 fs RMS phase jitter (measured with external crystal) meets the stringent <100 fs RMS requirement for PCIe Gen4 SRIS when combined with proper layout and termination - validated by Silicon Labs' PCIe compliance reports.