Skyworks Solutions Inc. SI5332AC09696-GM2R
- Part No.:
- SI5332AC09696-GM2R
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- -
- Datasheet:
-
SI5332AC09696-GM2R.pdf
- Description:
- IC CLOCK GENERATOR QFN
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Product details
Overview
SI5332AC09696-GM2R from Silicon Labs is an 8-output, factory-programmed, any-frequency clock generator with MultiSynth™ fractional synthesis, 190 fs RMS jitter (external crystal), differential/LVCMOS output format configurability per channel, and support for 5–333.33 MHz output frequencies. It serves as a high-precision timing source in Ethernet switch timing subsystems requiring multiple synchronous clocks.
For engineers reviewing the SI5332AC09696-GM2R datasheet, SI5332AC09696-GM2R pinout, SI5332AC09696-GM2R application, or SI5332AC09696-GM2R equivalent, key selection considerations include its 40-pin QFN package, 8-differential-output capability, embedded configuration via NVM, I²C programmability, and PCIe Gen4/SRIS compliance for low-jitter serial link timing.
Technical Context
The SI5332AC09696-GM2R implements a two-stage synthesis architecture: a wideband PLL locks to a 16–50 MHz external crystal (XA/XB), then feeds up to three independent MultiSynth fractional dividers and five integer dividers. Its cross-point mux routes synthesized frequencies to eight differential outputs grouped into Bank A (OUT0/OUT1), Bank B (OUT2/OUT3), and dedicated VDDO-supplied outputs OUT4–OUT7.
Each output supports user-selectable LVDS/LVPECL/HCSL/LVCMOS formats with programmable swing, polarity, and 35 ps-step skew control. Input selection is configurable via register or two universal HW pins (CLKIN_SEL[1:0]), and spread spectrum (down/center, 0.1–2.5%) is supported per MultiSynth path.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 8 differential clock outputs, organized across two banks and four dedicated outputs |
| Jitter (RMS) | 190 fs RMS (measured at 12 kHz–20 MHz offset, external crystal reference) |
| Output frequency range | 5–333.33 MHz differential; 5–170 MHz LVCMOS |
| Synthesis modes | Integer and fractional synthesis enabled on all outputs via MultiSynth technology |
| Input reference | External crystal (16–50 MHz) on XA/XB pins; no embedded crystal |
| Supply voltages | VDD core: 1.8/2.5/3.3 V; VDDO banks: 1.5/1.8/2.5/3.3 V for LVCMOS, 1.8/2.5/3.3 V for differential |
| Compliance | PCIe Gen1/2/3/4 and SRIS compliant for serial data link timing integrity |
Pinout & Package
SI5332AC09696-GM2R is housed in a 40-pin QFN package (6 mm × 6 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per the Si5332-GM2 variant and validated in the official Si5332 Data Sheet Rev. 1.1, Section 6.2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA/XB | Crystal input | Connects to fundamental-mode 16–50 MHz crystal; internal oscillator loads CL via register |
| OUT0–OUT7 | Differential clock outputs | Eight configurable outputs; OUT0/OUT1 share VDDO0, OUT2/OUT3 share VDDO1, OUT4–OUT7 each have dedicated VDDO |
| VDDO0–VDDO5 | Output supply rails | Independent voltage supplies per bank/output group; set logic levels and drive strength |
| SCLK/SDATA | I²C interface | Standard two-wire serial interface for in-system reconfiguration and status readback |
| OEb | Output enable | Active-low hardware control to disable all outputs synchronously without glitch |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth fractional synthesis | Enables exact non-integer frequency generation (e.g., 156.25 MHz, 212.5 MHz) on any output up to 250 MHz with zero ppm error |
| Per-output signal format selection | LVDS, LVPECL, HCSL, or LVCMOS configurable independently per output pair - eliminates need for external level translators |
| Configurable output skew | 35 ps step resolution across ±122.5 ps range per differential pair - enables precise inter-channel alignment for SerDes sampling |
| Multi-profile NVM storage | Up to 16 complete clock configurations stored in on-chip NVM; selected via hardware pins or I²C for rapid system boot mode switching |
| Synchronous output disable | Guarantees full-cycle disable/enable without runt pulses - critical for hot-swap and power-gating applications |
Applications
| 100G Ethernet Switch Timing | PCIe Gen4 Server Clock Tree |
|---|---|
Use Scenario: Provides synchronized 100G/200G line-rate clocks to multiple MAC/PHY ASICs and packet processors in modular data center switches. IC Role / Device Role / Timing Role: Centralized clock generator delivering phase-aligned 156.25 MHz, 312.5 MHz, and 625 MHz clocks with <200 fs jitter to meet IEEE 802.3bj jitter budgets. Use Value: Replaces 4–5 discrete oscillators and fanout buffers, reducing BOM count and PCB area while guaranteeing deterministic inter-clock skew ≤100 ps. | Use Scenario: Generates PCIe Gen4 reference clocks (100 MHz differential) and auxiliary clocks (25 MHz, 100 MHz LVCMOS) for CPU, GPU, and NVMe controller domains in rack-scale servers. IC Role / Device Role / Timing Role: Low-jitter, SRIS-compliant clock source meeting PCIe CEM 5.0 spec for root complex and endpoint timing margins. Use Value: Eliminates separate 100 MHz XO + fanout + level-shifter chain; supports dynamic frequency scaling via I²C during power state transitions. |
| 5G Small Cell Baseband Timing | Broadcast Video Synchronization |
Use Scenario: Supplies precisely aligned sampling clocks (122.88 MHz, 245.76 MHz) to dual ADC/DAC chains and FPGA-based digital front-end in compact 5G NR small cell units. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating telecom-grade jitter-clean clocks traceable to GPS-disciplined 10 MHz reference via CLKIN_2. Use Value: Achieves <100 fs integrated jitter (12 kHz–20 MHz) required for 256-QAM EVM performance; supports hitless holdover during GNSS outage via internal oscillator stability. | Use Scenario: Distributes SMPTE ST 2059-2–compliant PTP grandmaster clocks (27 MHz, 74.25 MHz, 148.5 MHz) across video encoder, decoder, and frame synchronizer modules in broadcast OB vans. IC Role / Device Role / Timing Role: Multi-format clock generator delivering LVDS and LVCMOS outputs simultaneously to mixed-voltage video ICs with sub-nanosecond inter-output skew. Use Value: Enables single-device replacement of legacy crystal + divider + translator solutions; simplifies FCC/CE radiated emissions certification via programmable spread spectrum on selected outputs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332BC09696-GM2R | Same 40-pin QFN package and 8-output architecture, but rated for 5–200 MHz max output (vs. 333.33 MHz); uses integer-only synthesis mode | Targeted at lower-frequency applications like SATA, USB 3.x, and legacy Ethernet where >200 MHz outputs are unnecessary | Select when design requires only integer-ratio clocks below 200 MHz and cost optimization is prioritized over ultra-wide frequency range |
| Si5341-A06609-GM | 12-output, 48-QFN clock generator with 150 fs RMS jitter (embedded crystal), higher integration including integrated LDOs and enhanced spread spectrum | Designed for high-end compute and AI accelerator timing where ultra-low jitter and >8 outputs are mandatory | Choose when system demands <160 fs jitter, 12+ outputs, or embedded crystal simplification - at higher cost and larger footprint |
Compared with SI5332AC09696-GM2R, Si5332BC09696-GM2R trades maximum output frequency and fractional synthesis for lower unit cost, while Si5341-A06609-GM delivers superior jitter and output count at the expense of package size and bill-of-materials complexity.
Availability
SI5332AC09696-GM2R is available at Aetrix Electronics and suitable for Ethernet switching, PCIe server timing, and 5G small cell baseband applications requiring stable component supply, long-term lifecycle assurance, and factory-programmed repeatability.
Supply support for SI5332AC09696-GM2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with deep expertise in high-performance clock generation and RF integration.
The Si5332 family was designed to replace multiple discrete clock sources in high-speed digital systems, enabling flexible, software-defined timing trees with sub-200 fs jitter and multi-voltage output support for heterogeneous SoC interfaces.
FAQ
What is the maximum output frequency supported by SI5332AC09696-GM2R?
The SI5332AC09696-GM2R supports differential output frequencies up to 333.33 MHz and LVCMOS outputs up to 170 MHz. This capability is enabled by its MultiSynth fractional synthesis architecture, which maintains 0 ppm frequency error across the full range. The device achieves this using a wideband PLL and high-resolution dividers, making it suitable for demanding applications such as 100G Ethernet and PCIe Gen4 timing.
Does SI5332AC09696-GM2R include an embedded crystal?
No, SI5332AC09696-GM2R does not include an embedded crystal. It is part of the Si5332A/B/C/D series, which requires an external 16–50 MHz fundamental-mode crystal connected to the XA/XB pins. The "A" suffix in SI5332AC09696-GM2R confirms external crystal operation, distinguishing it from Si5332E/F/G/H variants that integrate a 50 MHz MEMS crystal.
How many independent voltage domains does SI5332AC09696-GM2R support for its outputs?
SI5332AC09696-GM2R supports six independent VDDO supply pins (VDDO0–VDDO5), enabling mixed-supply operation across its eight differential outputs. Specifically, OUT0/OUT1 share VDDO0, OUT2/OUT3 share VDDO1, and OUT4–OUT7 each connect to dedicated VDDO2–VDDO5. This allows simultaneous LVDS (2.5 V), LVPECL (3.3 V), and LVCMOS (1.8 V) signaling on different outputs without level-shifting components.
Can SI5332AC09696-GM2R be reprogrammed after deployment?
Yes, SI5332AC09696-GM2R supports full in-system programming via its I²C interface (SCLK/SDATA pins). While factory-programmed with a ClockBuilder Pro configuration stored in NVM, all registers-including frequency, format, skew, and enable settings-can be modified dynamically. This enables runtime clock profile switching, field calibration, and firmware-driven timing adaptation without requiring hardware changes or reflashing.
Is SI5332AC09696-GM2R compliant with PCIe Gen4 timing requirements?
Yes, SI5332AC09696-GM2R is explicitly stated as PCIe Gen1/2/3/4 and SRIS compliant in the official Si5332 Data Sheet. Its 190 fs RMS jitter (12 kHz–20 MHz) meets the stringent phase jitter limits for PCIe Gen4 reference clocks, and its programmable spread spectrum helps reduce EMI in dense server backplanes. The device's synchronous output disable and low-skew capabilities further ensure robust link training and stability.
SI5332AC09696-GM2R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Not For New Designs
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Divider/Multiplier:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- -
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- -
SI5332AC09696-GM2R FAQ
1.How can I place an order for SI5332AC09696-GM2R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5332AC09696-GM2R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5332AC09696-GM2R reliable?
The price and inventory of SI5332AC09696-GM2R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332AC09696-GM2R is usually 5 days.
3.What payment methods are accepted for SI5332AC09696-GM2R?
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SI5332AC09696-GM2R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5332AC09696-GM2R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5332AC09696-GM2R?
For technical support, including SI5332AC09696-GM2R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332AC09696-GM2R requirements.
6.How does Aetrix verify that SI5332AC09696-GM2R is sourced from the original manufacturer or authorized distributors?
All SI5332AC09696-GM2R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332AC09696-GM2R meets industry standards.
7.What is the process for return or replacement of SI5332AC09696-GM2R?
All SI5332AC09696-GM2R units undergo pre-shipment inspection (PSI). If there is an issue with SI5332AC09696-GM2R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5332AC09696-GM2R part is unused and in its original packaging.
Return procedure for SI5332AC09696-GM2R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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