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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5332AD15661-GM2R

Name: SI5332AD15661-GM2R
Brand: Skyworks Solutions Inc.
SKU: SI5332AD15661-GM2R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5332AD15661-GM2R

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5332AD15661-GM2R.pdf

Description:: LOW JITTER, 8-OUTPUT, ANY-FREQUE

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Product details

Overview

SI5332AD15661-GM2R from Skyworks Solutions is an 8-output, programmable, low-jitter clock generator using MultiSynth™ fractional synthesis. It delivers up to 333.33 MHz differential outputs with 190 fs RMS phase jitter (external crystal), supports LVDS/LVPECL/HCSL/LVCMOS per-output configuration, and operates across –40 to +85 °C for Ethernet switch timing and PCIe Gen5/6 reference clocking.

For engineers reviewing the SI5332AD15661-GM2R datasheet, SI5332AD15661-GM2R pinout, SI5332AD15661-GM2R application, or SI5332AD15661-GM2R equivalent, key selection criteria include its 40-pin QFN package, dual fractional synthesis paths, independent VDDO banks, I²C programmability, and factory preprogrammed NVM configuration for drop-in deployment in mixed-voltage clock trees.

Technical Context

The SI5332AD15661-GM2R implements a wideband PLL coupled with two independent MultiSynth™ fractional synthesis engines and five integer dividers, enabling simultaneous generation of non-integer-related frequencies on up to eight differential outputs. Its cross-point mux routes any synthesized or divided frequency to any output bank.

It supports free-run mode via external 16–50 MHz crystal or synchronous mode via differential (10–250 MHz) or LVCMOS (10–170 MHz) inputs. Output banks A and B each share dedicated VDDO pins, allowing independent 1.8/2.5/3.3 V supply domains for mixed-signal interface compatibility.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 differential clock outputs (Si5332-GM2 variant)
Max output frequency	333.33 MHz differential; enables PCIe Gen6 reference clocks
Phase jitter (RMS)	190 fs (12 kHz–20 MHz), measured with external crystal input
Synthesis architecture	Dual fractional MultiSynth™ + 5 integer dividers; supports hitless frequency changes
Input support	External crystal (16–50 MHz), differential clock (10–250 MHz), LVCMOS (10–170 MHz)
Output format	User-configurable per output: LVDS, LVPECL, HCSL, or LVCMOS
Supply voltage	VDD core: 1.8/2.5/3.3 V; VDDO banks: 1.5/1.8/2.5/3.3 V (LVCMOS), 1.8/2.5/3.3 V (differential)

Pinout & Package

SI5332AD15661-GM2R is housed in a 40-pin, 6 × 6 mm QFN package (RoHS-6 compliant, GM2 designation). The package features exposed thermal pad, 0.5 mm pitch, and surface-mount land pattern per Skyworks document 206453A Section 8.2.

Pin/Terminal	Circuit Role	Design Meaning
OUT0 / OUT0b	Differential clock output pair	Bank A output; configurable signal format and VDDO0 supply
OUT1 / OUT1b	Differential clock output pair	Bank A output; independently routed via cross-point mux
OUT2 / OUT2b	Differential clock output pair	Bank A output; shares VDDO1 with OUT1/OUT1b
OUT3 / OUT3b	Differential clock output pair	Bank A output; supports HCSL/LVDS/LVPECL/LVCMOS
OUT4 / OUT4b	Differential clock output pair	Bank B output; dedicated VDDO3 supply
OUT5 / OUT5b	Differential clock output pair	Bank B output; supports independent integer division
OUT6 / OUT6b	Differential clock output pair	Bank B output; routed from MultiSynth0 or INT divider path
OUT7 / OUT7b	Differential clock output pair	Bank B output; enables synchronized multi-rate clock tree
VDDO0–VDDO5	Output driver supply pins	6 independent VDDO pins power 2 banks (A/B); allow mixed-voltage signaling
XA / XB	Crystal oscillator interface	Accepts 16–50 MHz fundamental-mode crystal; internal CL tuning supported
CLKIN_2 / CLKIN_2b	Differential input clock	10–250 MHz LVDS/LVPECL/HCSL; used for synchronous mode operation
SCLK / SDATA	I²C serial interface	Standard 400 kHz I²C bus for configuration and runtime reprogramming
OE	Output enable control	Hardware-controlled global output disable; supports power sequencing
INPUT1–INPUT7	Universal hardware input pins	Configurable in ClockBuilder Pro as OE, spread-spectrum enable, or input select

Key Features

Feature	Design Value
Dual fractional synthesis paths	Enables independent generation of two unrelated high-frequency clocks (e.g., 100 MHz + 156.25 MHz) without jitter coupling
Cross-point multiplexer	Routes any MultiSynth or integer-divided frequency to any output bank-critical for flexible clock tree mapping
Multi-profile NVM storage	Stores up to 16 configurations; allows fast switching between system modes (e.g., low-power vs. full-bandwidth)
Adjustable output-output delay	Per-output skew control enables precise timing alignment across SerDes lanes or memory interfaces
Spread spectrum modulation	Down- or center-spread from 0.1% to 2.5% at 30–33 kHz reduces EMI in dense PCB layouts

Applications

Server PCIe Timing	Ethernet Switch Synchronization
Use Scenario: Generating PCIe Gen5/6 reference clocks (100 MHz, 125 MHz, 250 MHz) and auxiliary clocks (e.g., 33.33 MHz for BMC) in dual-socket servers. IC Role / Device Role / Timing Role: Primary clock generator replacing multiple oscillators and fanout buffers; provides deterministic phase relationships across CPU, GPU, and NIC domains. Use Value: Eliminates board-level clock skew and reduces component count by consolidating 8 discrete timing sources into one IC with <190 fs jitter.	Use Scenario: Delivering synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks to 10G/25G/100G Ethernet PHYs and packet processors in layer-3 switches. IC Role / Device Role / Timing Role: Centralized timing hub with independent output banks driving different voltage domains (1.8 V PHYs, 3.3 V management MCU). Use Value: Enables deterministic inter-PHY skew control and eliminates need for external level shifters via per-bank VDDO flexibility.
Broadcast Video Genlock	Industrial Embedded Computing
Use Scenario: Providing SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks with sub-10 ps inter-output skew for multi-camera capture systems. IC Role / Device Role / Timing Role: Genlock master clock generator with ultra-low jitter and programmable output delay for frame synchronization. Use Value: Meets broadcast-grade timing stability requirements (<±50 ppb frequency accuracy, <200 fs jitter) without external jitter cleaners.	Use Scenario: Supplying 50 MHz system clock, 25 MHz Ethernet MAC clock, and 100 MHz FPGA fabric clock in ruggedized edge controllers with extended temperature operation. IC Role / Device Role / Timing Role: Single-chip timing solution supporting –40 to +85 °C operation and mixed-signal I/O (LVCMOS for MCU, LVDS for FPGA). Use Value: Reduces BOM cost and layout complexity while maintaining timing integrity under thermal cycling and EMI stress.

Server PCIe Timing

Ethernet Switch Synchronization

Use Scenario: Generating PCIe Gen5/6 reference clocks (100 MHz, 125 MHz, 250 MHz) and auxiliary clocks (e.g., 33.33 MHz for BMC) in dual-socket servers.

IC Role / Device Role / Timing Role: Primary clock generator replacing multiple oscillators and fanout buffers; provides deterministic phase relationships across CPU, GPU, and NIC domains.

Use Value: Eliminates board-level clock skew and reduces component count by consolidating 8 discrete timing sources into one IC with <190 fs jitter.

Use Scenario: Delivering synchronized 156.25 MHz, 312.5 MHz, and 625 MHz clocks to 10G/25G/100G Ethernet PHYs and packet processors in layer-3 switches.

IC Role / Device Role / Timing Role: Centralized timing hub with independent output banks driving different voltage domains (1.8 V PHYs, 3.3 V management MCU).

Use Value: Enables deterministic inter-PHY skew control and eliminates need for external level shifters via per-bank VDDO flexibility.

Broadcast Video Genlock

Industrial Embedded Computing

Use Scenario: Providing SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks with sub-10 ps inter-output skew for multi-camera capture systems.

IC Role / Device Role / Timing Role: Genlock master clock generator with ultra-low jitter and programmable output delay for frame synchronization.

Use Value: Meets broadcast-grade timing stability requirements (<±50 ppb frequency accuracy, <200 fs jitter) without external jitter cleaners.

Use Scenario: Supplying 50 MHz system clock, 25 MHz Ethernet MAC clock, and 100 MHz FPGA fabric clock in ruggedized edge controllers with extended temperature operation.

IC Role / Device Role / Timing Role: Single-chip timing solution supporting –40 to +85 °C operation and mixed-signal I/O (LVCMOS for MCU, LVDS for FPGA).

Use Value: Reduces BOM cost and layout complexity while maintaining timing integrity under thermal cycling and EMI stress.

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332BD15661-GM2R	Same 40-pin QFN package and pinout; differs in NVM configuration (B-grade supports integer-only synthesis up to 200 MHz)	Limited to integer synthesis; unsuitable for non-integer ratios like 156.25 MHz from 25 MHz reference	Select SI5332AD15661-GM2R when fractional synthesis and >200 MHz output capability are required.
LMK04832RHAR	14-output, dual-loop PLL architecture; higher power; requires external loop filter; 115 fs RMS jitter (with clean reference)	Targeted at RF and instrumentation where ultra-low jitter dominates over integration density	Choose LMK04832RHAR only if sub-120 fs jitter is mandatory and board space for external components is available.

Compared with Si5332BD15661-GM2R, SI5332AD15661-GM2R supports fractional synthesis up to 333.33 MHz and delivers lower jitter in integer+fractional mode; versus LMK04832RHAR, it offers higher integration, smaller footprint, and simpler layout at the cost of slightly higher jitter-making it optimal for high-density networking and compute platforms.

Availability

SI5332AD15661-GM2R is available at Aetrix Electronics and suitable for Ethernet switch timing, PCIe Gen5/6 reference clocking, and broadcast video genlock applications requiring stable component supply, long-term lifecycle assurance, and factory-programmed configuration traceability.

Supply support for SI5332AD15661-GM2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure and mobility markets.

The SI5332AD15661-GM2R belongs to Skyworks' Si5332 family of any-frequency clock generators, designed specifically to replace multiple discrete oscillators and fanout buffers in high-speed digital systems including data centers, 5G infrastructure, and professional AV equipment.

FAQ

What is the maximum differential output frequency supported by the SI5332AD15661-GM2R?

The SI5332AD15661-GM2R supports differential output frequencies up to 333.33 MHz. This capability enables direct generation of PCIe Gen6 reference clocks (333.33 MHz) and 100G Ethernet PAM4 sampling clocks without external frequency multiplication. The limit applies regardless of input source-whether external crystal, embedded crystal, or differential clock input-and is verified across the full –40 to +85 °C operating range.

Does the SI5332AD15661-GM2R include an embedded crystal?

No, the SI5332AD15661-GM2R does not include an embedded crystal. It belongs to the Si5332A/D grade series, which requires an external 16–50 MHz fundamental-mode crystal connected to XA/XB pins. Embedded crystal variants (e.g., Si5332E/F/G/H/L) use a factory-integrated 50 MHz MEMS resonator and carry different part number suffixes (e.g., -GM2R becomes -GM2R-E).

How many independent power domains does the SI5332AD15661-GM2R support for its outputs?

The SI5332AD15661-GM2R supports six independent VDDO supply pins (VDDO0–VDDO5), grouped into two banks: Bank A (OUT0–OUT3) and Bank B (OUT4–OUT7). Each bank can be powered at 1.8 V, 2.5 V, or 3.3 V for differential outputs-or 1.5/1.8/2.5/3.3 V for LVCMOS-enabling true mixed-voltage clock distribution without level shifters.

Can the SI5332AD15661-GM2R generate PCIe Gen5 and Gen6 reference clocks?

Yes, the SI5332AD15661-GM2R is explicitly PCIe Gen1/2/3/4/5/6 and SRIS compliant. It generates 100 MHz (Gen3/4), 125 MHz (Gen5), and 333.33 MHz (Gen6) reference clocks with ≤190 fs RMS phase jitter (12 kHz–20 MHz), meeting PCI-SIG jitter budget requirements for all generations. Its fractional synthesis ensures zero ppm frequency error-critical for Gen6 link training stability.

Is the SI5332AD15661-GM2R preprogrammed at the factory?

Yes, SI5332AD15661-GM2R is a factory-programmed device. Its NVM contains a ClockBuilder Pro–generated configuration (NVM code D15661), enabling immediate operation at power-up without host processor intervention. The configuration includes output frequencies, formats, VDDO assignments, and spread-spectrum settings-all validated during manufacturing test.

SI5332AD15661-GM2R Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: -

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5332AD15661-GM2R FAQ

1.How can I place an order for SI5332AD15661-GM2R through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5332AD15661-GM2R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5332AD15661-GM2R reliable?

The price and inventory of SI5332AD15661-GM2R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332AD15661-GM2R is usually 5 days.

3.What payment methods are accepted for SI5332AD15661-GM2R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332AD15661-GM2R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5332AD15661-GM2R?

SI5332AD15661-GM2R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5332AD15661-GM2R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5332AD15661-GM2R?

For technical support, including SI5332AD15661-GM2R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332AD15661-GM2R requirements.

6.How does Aetrix verify that SI5332AD15661-GM2R is sourced from the original manufacturer or authorized distributors?

All SI5332AD15661-GM2R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332AD15661-GM2R meets industry standards.

7.What is the process for return or replacement of SI5332AD15661-GM2R?

All SI5332AD15661-GM2R units undergo pre-shipment inspection (PSI). If there is an issue with SI5332AD15661-GM2R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5332AD15661-GM2R part is unused and in its original packaging.

Return procedure for SI5332AD15661-GM2R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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