Skyworks Solutions Inc. SI5332BC09765-GM1

Overview

SI5332BC09765-GM1 from Silicon Labs is a 6-output, 32-pin QFN programmable clock generator using MultiSynth™ fractional synthesis to deliver any-frequency outputs up to 333.33 MHz with 190 fs RMS phase jitter (external crystal). It supports LVDS/LVPECL/HCSL/LVCMOS per-output signal formats, independent VDDO per output bank, and operates across –40 to +85 °C for Ethernet switch timing and server clock tree consolidation.

For engineers reviewing the SI5332BC09765-GM1 datasheet, SI5332BC09765-GM1 pinout, SI5332BC09765-GM1 application, or SI5332BC09765-GM1 equivalent, key selection criteria include differential output count (6), external crystal input support (16–50 MHz), PCIe Gen1–4/SRIS compliance, I²C programmability, and factory pre-programmability via ClockBuilder Pro™.

Technical Context

The SI5332BC09765-GM1 implements a two-stage synthesis architecture: a wideband PLL locks to an external 16–50 MHz crystal (XA/XB pins), then feeds up to three independent MultiSynth fractional dividers and five integer dividers. Its cross-point mux routes any synthesized or divided frequency to any of six differential outputs.

Each output features user-configurable format (LVDS/LVPECL/HCSL/LVCMOS), adjustable skew (±122.5 ps in 35 ps steps), synchronous enable/disable, and independent VDDO supply (1.5/1.8/2.5/3.3 V), enabling mixed-voltage clock distribution in multi-rail systems without level shifters.

Key Specifications

Pinout & Package

SI5332BC09765-GM1 uses a 32-pin QFN package (5 mm × 5 mm, 0.5 mm pitch) with exposed thermal pad. Pin functions are defined per ClockBuilder Pro configuration; hardware inputs (Input1–Input5) are user-assignable for OE, spread spectrum enable, or input selection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable clock generator applications.

Compared with Si5332AC09765-GM1, SI5332BC09765-GM1 trades 15 fs jitter for external crystal configurability and broader input range (16–50 MHz vs fixed 50 MHz). Versus LMK04832RHAR, it delivers adequate jitter for PCIe Gen4 at half the pin count and no loop filter components - reducing layout complexity and cost in mid-channel-count systems.

Availability

SI5332BC09765-GM1 is available at Aetrix Electronics and suitable for Ethernet switches, server clock trees, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.

Supply support for SI5332BC09765-GM1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with leadership in high-performance clock generation and low-power connectivity.

The Si5332 family was designed to replace multiple fixed-frequency oscillators and clock buffers with a single programmable device, targeting datacenter, telecom, and broadcast applications demanding flexible, low-jitter timing.

FAQ

What is the maximum differential output frequency supported by the SI5332BC09765-GM1?

The SI5332BC09765-GM1 supports differential output frequencies up to 333.33 MHz. This specification is confirmed in the Si5332 Data Sheet Section 1 (Features List) and Section 5 (Electrical Specifications), and enables direct clocking of DDR4/5 memory interfaces, 10G/25G Ethernet PHYs, and high-speed SerDes blocks without external frequency multiplication.

Does the SI5332BC09765-GM1 include an embedded crystal?

No, the SI5332BC09765-GM1 does not include an embedded crystal. It belongs to the Si5332B grade (external crystal variant), requiring connection of a 16–50 MHz fundamental-mode crystal to the XA/XB pins. Embedded crystal variants use Si5332E/F/G/H part numbering and carry "E" or "F" suffixes.

How many universal hardware input pins does the SI5332BC09765-GM1 have?

The SI5332BC09765-GM1 has five universal hardware input pins (Input1–Input5), as documented in Figure 3.3 (Block Diagram for 6-Output Si5332 in 32-QFN) and Section 3.7 of the Si5332 Data Sheet. These pins are user-configurable in ClockBuilder Pro for functions including output enable (OE#), spread spectrum enable, or input clock selection.

Is the SI5332BC09765-GM1 PCIe Gen4-compliant?

Yes, the SI5332BC09765-GM1 is PCIe Gen1/2/3/4 and SRIS compliant, as explicitly stated in the "Features List" (page 4) of the Si5332 Data Sheet. Its 190 fs RMS phase jitter (measured with external crystal) meets the PCIe Gen4 SRIS requirement of ≤500 fs at 100 MHz, making it suitable for root complex and endpoint timing in high-speed compute platforms.

Can the SI5332BC09765-GM1 generate both LVDS and LVPECL outputs simultaneously?

Yes, the SI5332BC09765-GM1 supports simultaneous LVDS and LVPECL outputs. Each of its six differential output pairs (OUT0–OUT5) can be independently configured for LVDS, LVPECL, HCSL, or LVCMOS via ClockBuilder Pro or I²C register writes - enabling mixed-signal timing in systems with diverse PHY requirements without external level translation.