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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5332BD15689-GM1

Name: SI5332BD15689-GM1
Brand: Skyworks Solutions Inc.
SKU: SI5332BD15689-GM1
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5332BD15689-GM1

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 32-VFQFN Exposed Pad

Datasheet:: SI5332BD15689-GM1.pdf

Description:: LOW JITTER, 6-OUTPUT, ANY-FREQUE

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Product details

Overview

SI5332BD15689-GM1 from Skyworks is a 6-output, programmable any-frequency clock generator with MultiSynth™ fractional synthesis, delivering 190 fs RMS phase jitter (external crystal), 5–333.33 MHz differential output range, and user-configurable LVDS/LVPECL/HCSL/LVCMOS signal formats per output. It serves as a high-precision timing source in PCIe Gen1–6-compliant server and networking systems.

For engineers reviewing the SI5332BD15689-GM1 datasheet, SI5332BD15689-GM1 pinout, SI5332BD15689-GM1 application, or SI5332BD15689-GM1 equivalent, this device supports mixed-supply clock distribution across six independent differential outputs, factory-programmed configuration via ClockBuilder Pro, and I²C-based in-system reconfiguration - critical for multi-protocol timing consolidation in dense embedded platforms.

Technical Context

The SI5332BD15689-GM1 implements a wideband PLL paired with two independent MultiSynth fractional synthesis paths and five integer dividers, enabling simultaneous generation of non-integer-related frequencies up to 333.33 MHz on up to six differential outputs. Its architecture includes a cross-point multiplexer routing any synthesized or reference frequency to any output path.

It operates in free-run mode using an external 16–50 MHz crystal (XA/XB) or synchronous mode with differential (10–250 MHz) or LVCMOS (10–170 MHz) inputs. Output banks are isolated by individual VDDO pins, supporting mixed-voltage operation (1.5/1.8/2.5/3.3 V) per driver - essential for heterogeneous SoC interface requirements.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	6 differential clock outputs, each with dedicated VDDO supply pin for independent voltage assignment.
Phase Jitter (RMS)	190 fs (12 kHz–20 MHz integration bandwidth), measured with external crystal reference - meets PCIe Gen5/6 jitter budgets.
Output Frequency Range	Differential: 5–333.33 MHz; supports integer and fractional synthesis with 0 ppm error - enables exact clock tree replication.
Input Reference	External crystal: 16–50 MHz at XA/XB; no embedded crystal - requires external XTAL and load capacitors.
Signal Format per Output	User-selectable LVDS, LVPECL, HCSL, or LVCMOS - eliminates need for external level-shifting or buffer ICs.
Supply Voltages	VDD core: 1.8/2.5/3.3 V; VDDO per output: 1.5/1.8/2.5/3.3 V - supports mixed-voltage SoC clocking without level translators.
Interface & Configuration	I²C serial interface (up to 400 kHz); factory-programmed NVM stores default configuration - enables zero-latency power-up operation.

Pinout & Package

SI5332BD15689-GM1 uses a 32-pin, 5×5 mm QFN/LGA package (RoHS-6 compliant) with exposed thermal pad. Pin assignments follow the Si5332-GM1 32-pin functional block diagram: six differential output pairs (OUT0/OUT0b through OUT5/OUT5b), five universal hardware input pins (Input1–Input5), I²C SCLK/SDATA, XTAL XA/XB, CLKIN_2/CLKIN_2#, VDD/VDDO rails, and GND/PGND.

Pin/Terminal	Circuit Role	Design Meaning
OUT0 / OUT0b	Differential clock output pair	Configurable format (LVDS/LVPECL/HCSL/LVCMOS); powered by dedicated VDDO0 - enables independent voltage scaling per output.
OUT1 / OUT1b	Differential clock output pair	Independent MultiSynth or integer divider sourcing; VDDO1 decoupled - isolates noise between clock domains.
OUT2 / OUT2b	Differential clock output pair	Routed via cross-point mux; supports glitchless on-the-fly frequency change - critical for dynamic PCIe link training.
OUT3 / OUT3b	Differential clock output pair	Driven from same synthesis path options as OUT0–OUT2; VDDO3 assignable - supports mixed-signal SoC interfaces.
OUT4 / OUT4b	Differential clock output pair	Configurable skew settings; supports synchronous disable - enables precise timing alignment in multi-lane SerDes.
OUT5 / OUT5b	Differential clock output pair	Final output bank; independently enabled/disabled via register or HW pin - allows runtime clock gating for power management.
XA / XB	Crystal oscillator terminals	Accepts 16–50 MHz fundamental-mode crystal; internal CL selectable (2.5–21.5 pF) - eliminates external load caps in most designs.
CLKIN_2 / CLKIN_2#	Differential input clock	Supports LVPECL/LVDS/HCSL; AC-coupled; 10–250 MHz range - enables fallback to system reference clock if crystal fails.
SCLK / SDATA	I²C serial interface	Standard two-wire bus (400 kHz max); used for in-system programming and real-time register updates - enables field firmware updates.
Input1–Input5	Universal hardware control pins	Configurable as OE, spread-spectrum enable, input select, or I²C address - reduces need for external GPIOs in compact layouts.

Key Features

Feature	Design Value
Any-frequency synthesis	Generates exact integer and non-integer frequencies up to 333.33 MHz on all 6 outputs with 0 ppm error - replaces multiple fixed-frequency oscillators.
MultiSynth fractional synthesis	Two independent fractional synthesis paths enable concurrent generation of unrelated frequencies (e.g., 156.25 MHz + 250 MHz + 100 MHz) - simplifies clock tree design.
Per-output signal format	Each output individually set to LVDS, LVPECL, HCSL, or LVCMOS - eliminates external level shifters and reduces BOM count.
Mixed-supply output banks	Six dedicated VDDO pins allow different supply voltages per output (1.5/1.8/2.5/3.3 V) - matches diverse SoC I/O standards without translation.
PCIe Gen1–6 compliance	Meets jitter, spread spectrum, and protocol timing requirements for all generations - validated for use in root complex and endpoint applications.
Factory-programmed NVM	Custom configuration stored in on-chip non-volatile memory; powers up with full clock tree active - removes boot-time I²C initialization delay.

Applications

Server PCIe Timing	Ethernet Switch Clocking
Use Scenario: Generating synchronized 100 MHz, 125 MHz, and 156.25 MHz clocks for CPU, GPU, and NIC PCIe Gen4/5 links in 1U rack servers. IC Role / Device Role / Timing Role: Primary clock generator providing low-jitter, multi-frequency timing with independent output control per PCIe lane group. Use Value: Eliminates 3–4 discrete oscillators and buffers; reduces board area by 40% and improves timing margin by 12 ps RMS jitter reduction vs. legacy solutions.	Use Scenario: Delivering 250 MHz SerDes reference, 156.25 MHz Ethernet PHY, and 100 MHz management interface clocks in 10G/25G/100G switches. IC Role / Device Role / Timing Role: Consolidated timing hub synchronizing switch fabric, packet processor, and PHY layers with sub-200 fs jitter. Use Value: Enables single-device clock tree for multi-rate Ethernet; supports hitless frequency switching during link renegotiation.
Broadcast Video Sync	Industrial Embedded Control
Use Scenario: Providing SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks for camera ingest, processing, and playback subsystems. IC Role / Device Role / Timing Role: Precision timing source meeting ±20 ppb accuracy and <1 ns phase wander for broadcast-grade video synchronization. Use Value: Replaces TCXO + divider chains; achieves <500 fs integrated jitter over 12 kHz–20 MHz - exceeds SMPTE ST 2059-2 Class A requirements.	Use Scenario: Supplying 50 MHz FPGA fabric clock, 25 MHz ADC sampling clock, and 10 MHz real-time controller reference in medical imaging or test equipment. IC Role / Device Role / Timing Role: Configurable clock generator supporting mixed-voltage I/O (1.8 V FPGA, 3.3 V ADC, 2.5 V MCU) from one IC. Use Value: Reduces power supply complexity; enables independent output enable/disable for dynamic power gating during idle states.

Server PCIe Timing

Ethernet Switch Clocking

Use Scenario: Generating synchronized 100 MHz, 125 MHz, and 156.25 MHz clocks for CPU, GPU, and NIC PCIe Gen4/5 links in 1U rack servers.

IC Role / Device Role / Timing Role: Primary clock generator providing low-jitter, multi-frequency timing with independent output control per PCIe lane group.

Use Value: Eliminates 3–4 discrete oscillators and buffers; reduces board area by 40% and improves timing margin by 12 ps RMS jitter reduction vs. legacy solutions.

Use Scenario: Delivering 250 MHz SerDes reference, 156.25 MHz Ethernet PHY, and 100 MHz management interface clocks in 10G/25G/100G switches.

IC Role / Device Role / Timing Role: Consolidated timing hub synchronizing switch fabric, packet processor, and PHY layers with sub-200 fs jitter.

Use Value: Enables single-device clock tree for multi-rate Ethernet; supports hitless frequency switching during link renegotiation.

Broadcast Video Sync

Industrial Embedded Control

Use Scenario: Providing SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz reference clocks for camera ingest, processing, and playback subsystems.

IC Role / Device Role / Timing Role: Precision timing source meeting ±20 ppb accuracy and <1 ns phase wander for broadcast-grade video synchronization.

Use Value: Replaces TCXO + divider chains; achieves <500 fs integrated jitter over 12 kHz–20 MHz - exceeds SMPTE ST 2059-2 Class A requirements.

Use Scenario: Supplying 50 MHz FPGA fabric clock, 25 MHz ADC sampling clock, and 10 MHz real-time controller reference in medical imaging or test equipment.

IC Role / Device Role / Timing Role: Configurable clock generator supporting mixed-voltage I/O (1.8 V FPGA, 3.3 V ADC, 2.5 V MCU) from one IC.

Use Value: Reduces power supply complexity; enables independent output enable/disable for dynamic power gating during idle states.

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332AD15689-GM1	Same 6-output 32-pin package and MultiSynth architecture, but uses external crystal only (no embedded crystal option); identical 190 fs jitter spec.	Targeted for cost-sensitive designs where crystal BOM is managed externally; lacks embedded 50 MHz crystal variant.	Select when external crystal layout is already defined and lowest unit cost is prioritized over footprint reduction.
LMK04832RHAT	6-output jitter cleaner with dual-loop PLL; higher 115 fs RMS jitter but requires external VCXO; no fractional synthesis on all outputs.	Better for ultra-low-jitter cleaning of noisy references; less flexible for arbitrary frequency generation than Si5332BD15689-GM1.	Choose when input reference is noisy and jitter cleaning is primary requirement, not multi-frequency synthesis.

Compared with Si5332AD15689-GM1, the SI5332BD15689-GM1 offers identical synthesis capability but belongs to the B-grade family with optimized integer/fractional mode support; versus LMK04832RHAT, it trades absolute jitter floor for broader frequency agility and integrated configuration - making it superior for PCIe and Ethernet clock tree consolidation.

Availability

SI5332BD15689-GM1 is available at Aetrix Electronics and suitable for server motherboard design, Ethernet switch timing, broadcast video synchronization, and industrial embedded control requiring stable component supply across extended production cycles.

Supply support for SI5332BD15689-GM1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The SI5332BD15689-GM1 belongs to Skyworks' Si5332 family of any-frequency clock generators, designed specifically to replace multiple discrete timing components in high-speed computing, networking, and communications infrastructure.

FAQ

What is the maximum output frequency supported by the SI5332BD15689-GM1?

The SI5332BD15689-GM1 supports differential output frequencies from 5 MHz to 333.33 MHz. This upper limit applies to both integer and fractional synthesis modes and is verified across the full –40 °C to +85 °C operating temperature range. The device achieves 0 ppm frequency synthesis error at all supported frequencies, making it suitable for PCIe Gen6 and 100G Ethernet applications requiring exact clock rates.

Does the SI5332BD15689-GM1 include an embedded crystal?

No, the SI5332BD15689-GM1 does not include an embedded crystal. It is part of the Si5332B grade, which requires an external 16–50 MHz fundamental-mode crystal connected to the XA/XB pins. Embedded crystal variants (e.g., Si5332E/F/G/H/L) are separate part numbers; this device relies on external crystal termination and supports internal load capacitance tuning from 2.5 pF to 21.5 pF.

How many independent voltage supplies does the SI5332BD15689-GM1 support for its outputs?

The SI5332BD15689-GM1 provides six dedicated VDDO pins - one per differential output pair (VDDO0 through VDDO5) - enabling independent supply voltage assignment. Each VDDO can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, allowing direct interfacing with mixed-voltage SoCs, FPGAs, and PHYs without external level shifters or regulators.

Can the SI5332BD15689-GM1 generate PCIe Gen5-compliant clocks?

Yes, the SI5332BD15689-GM1 is explicitly designed to meet PCIe Gen1 through Gen6 specifications, including jitter, spread spectrum, and protocol timing requirements. Its 190 fs RMS phase jitter (12 kHz–20 MHz) falls well below the PCIe Gen5 specification limit of 500 fs RMS, and it supports down-spread and center-spread spectrum modulation from 0.1% to 2.5% at 30–33 kHz.

What configuration software is required for the SI5332BD15689-GM1?

ClockBuilder Pro™ software is required to configure the SI5332BD15689-GM1. It enables full parameter definition (input/output frequencies, formats, voltage rails, spread spectrum), generates a custom part number (e.g., SI5332BD15689-GM1), and produces factory-programmable NVM images. Devices ordered with that custom part number are preprogrammed at no additional cost, ensuring immediate operation upon power-up.

SI5332BD15689-GM1 Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 32-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: -

Type:: Clock Generator

PLL:: Yes

Input:: Clock, Crystal, LVCMOS

Output:: HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 2:6

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 200MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C (TA)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 32-QFN (5x5)

SI5332BD15689-GM1 FAQ

1.How can I place an order for SI5332BD15689-GM1 through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5332BD15689-GM1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5332BD15689-GM1 reliable?

The price and inventory of SI5332BD15689-GM1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332BD15689-GM1 is usually 5 days.

3.What payment methods are accepted for SI5332BD15689-GM1?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332BD15689-GM1 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5332BD15689-GM1?

SI5332BD15689-GM1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5332BD15689-GM1 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5332BD15689-GM1?

For technical support, including SI5332BD15689-GM1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332BD15689-GM1 requirements.

6.How does Aetrix verify that SI5332BD15689-GM1 is sourced from the original manufacturer or authorized distributors?

All SI5332BD15689-GM1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332BD15689-GM1 meets industry standards.

7.What is the process for return or replacement of SI5332BD15689-GM1?

All SI5332BD15689-GM1 units undergo pre-shipment inspection (PSI). If there is an issue with SI5332BD15689-GM1, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5332BD15689-GM1 part is unused and in its original packaging.

Return procedure for SI5332BD15689-GM1:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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