Skyworks Solutions Inc. SI5332BD15705-GM1
- Part No.:
- SI5332BD15705-GM1
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
SI5332BD15705-GM1.pdf
- Description:
- LOW JITTER, 6-OUTPUT, ANY-FREQUE
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5332BD15705-GM1 from Skyworks is a 6-output, any-frequency programmable clock generator with MultiSynth™ fractional synthesis, delivering 190 fs RMS phase jitter (external crystal), 5–333.33 MHz differential output range, and support for LVDS/LVPECL/HCSL/LVCMOS signal formats per output. It serves as a high-precision timing source in PCIe Gen1–6-compliant server and networking systems requiring multiple synchronized clocks from a single device.
For engineers reviewing the SI5332BD15705-GM1 datasheet, SI5332BD15705-GM1 pinout, SI5332BD15705-GM1 application, or SI5332BD15705-GM1 equivalent, this page provides verified technical context, package mapping to 32-pin QFN/LGA, confirmed 6-differential-output architecture, I²C configurability, and real-world selection guidance against comparable clock generators.
Technical Context
The SI5332BD15705-GM1 implements a wideband PLL paired with two independent MultiSynth fractional synthesis paths and up to five integer dividers, enabling simultaneous generation of non-integer-related frequencies across its six differential outputs. Its cross-point multiplexer routes any synthesized or divided frequency to any output bank.
This variant uses an external 16–50 MHz crystal input (XA/XB) and supports free-run operation only - no embedded crystal. Each of the six outputs has dedicated VDDO pins, allowing independent supply voltages (1.8/2.5/3.3 V) per driver for mixed-signal system integration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 6 differential clock outputs, each configurable as LVDS, LVPECL, HCSL, or dual LVCMOS |
| Phase jitter (RMS) | 190 fs (measured over 12 kHz–20 MHz offset; external crystal reference) |
| Output frequency range | 5–333.33 MHz differential; 5–170 MHz LVCMOS - enables PCIe Gen1–6, Ethernet, and SerDes clocking |
| Synthesis architecture | Two independent MultiSynth fractional paths + five integer dividers - supports arbitrary frequency combinations without error |
| Input reference | External crystal only (16–50 MHz on XA/XB); no embedded crystal - requires external XTAL layout per Skyworks guidelines |
| Supply flexibility | Dedicated VDDO per output (1.8/2.5/3.3 V); core VDD = 1.8/2.5/3.3 V - supports mixed-voltage board domains |
| Interface & configuration | I²C serial interface; factory-programmed NVM with ClockBuilder Pro-generated configuration - no runtime host firmware required |
Pinout & Package
SI5332BD15705-GM1 is housed in a 5×5 mm, 32-pin QFN or LGA package (RoHS-6 compliant, GM suffix). The package supports exposed thermal pad for enhanced thermal performance in high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OUT0 / OUT0b | Differential clock output pair | Configurable signal format (LVDS/LVPECL/HCSL/LVCMOS); dedicated VDDO0 supply |
| OUT1 / OUT1b | Differential clock output pair | Independent format and voltage control via VDDO1; routed through cross-point MUX |
| OUT2 / OUT2b | Differential clock output pair | Supports glitchless frequency change; driven by MultiSynth0 or INT divider path |
| OUT3 / OUT3b | Differential clock output pair | Each output has individual VDDO3; enables mixed-supply clock distribution |
| OUT4 / OUT4b | Differential clock output pair | Programmable skew and enable/disable per output - critical for SerDes lane alignment |
| OUT5 / OUT5b | Differential clock output pair | Final output bank; supports spread spectrum (0.1–2.5% down/center) for EMI reduction |
| XA / XB | Crystal oscillator input | Accepts 16–50 MHz fundamental-mode crystal; internal CL tuning (2.5–21.5 pF) |
| SCLK / SDATA | I²C serial interface | Standard 100/400 kHz I²C bus; used for in-system reconfiguration or field updates |
| VDD / VSS | Core power & ground | 1.8/2.5/3.3 V core supply; separate from output drivers - improves PSRR and jitter immunity |
| CLKIN_2 / CLKIN_2b | Optional differential clock input | Not enabled in SI5332BD15705-GM1 - configured for crystal-only mode per NVM programming |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Generates exact output frequencies (e.g., 100.000 MHz, 156.25 MHz, 257.8125 MHz) with 0 ppm error using MultiSynth |
| Per-output signal format | Each of 6 outputs independently set to LVDS, LVPECL, HCSL, or LVCMOS - eliminates need for external level shifters |
| Independent VDDO supplies | 6 dedicated VDDO pins allow concurrent 1.8 V, 2.5 V, and 3.3 V clock domains - simplifies mixed-voltage SoC interfacing |
| PCIe Gen1–6 compliance | Meets jitter, slew rate, and spectral mask requirements for all generations - validated with reference clock trees |
| Factory-programmed NVM | Custom ClockBuilder Pro configuration stored in one-time-programmable memory - powers up with full clock tree active |
Applications
| Server Clock Tree | 5G Small Cell Baseband |
|---|---|
Use Scenario: Generating synchronous clocks for CPU, memory controller, PCIe root complex, and NIC in dual-socket x86 servers. IC Role / Device Role / Timing Role: Primary clock generator replacing 4–5 discrete oscillators and fanout buffers. Use Value: Reduces BOM count and layout area while maintaining <200 fs jitter across all 6 outputs for Gen5/Gen6 PCIe compliance. |
Use Scenario: Providing low-jitter reference clocks to FPGA-based baseband processors and RF transceivers in compact 5G small cell units. IC Role / Device Role / Timing Role: Central timing hub distributing 30.72 MHz, 122.88 MHz, and 245.76 MHz to ADC/DAC and digital front-end blocks. Use Value: Enables deterministic latency and sub-100 ps inter-channel skew between data converters and processing logic. |
| Ethernet Switch ASIC Timing | Broadcast Video Synchronization |
Use Scenario: Delivering precise 156.25 MHz, 312.5 MHz, and 625 MHz clocks to multi-port 10/25/100 GbE switch ASICs and PHYs. IC Role / Device Role / Timing Role: High-stability clock source meeting IEEE 802.3bj/ck jitter budgets for PAM4 signaling. Use Value: Achieves <0.3 UI peak-to-peak jitter at 100 GbE line rates, directly supporting forward error correction margin. |
Use Scenario: Synchronizing frame timing across SMPTE ST 2110 IP video encoders, decoders, and transport gateways in broadcast studios. IC Role / Device Role / Timing Role: Master reference generator for 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with ultra-low phase noise. Use Value: Prevents lip-sync drift and frame buffer underruns by maintaining <1 ps RMS jitter across all video domain clocks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332AD15705-GM1 | Same 32-pin package and 6-output architecture, but uses embedded 50 MHz crystal - eliminates external XTAL and associated layout constraints. | Preferred where board space is constrained and crystal placement/layout complexity must be avoided. | Select Si5332AD15705-GM1 if embedded crystal simplifies design; SI5332BD15705-GM1 retains full external crystal flexibility and lower cost. |
| LMK04832RHAR | 6-output, dual-loop PLL architecture with JESD204B support; higher power consumption (220 mW vs. ~130 mW); no MultiSynth fractional synthesis per output. | Better suited for JESD204B deterministic latency applications; less flexible for arbitrary frequency combinations. | Choose LMK04832RHAR only when JESD204B subclass 1 timing is mandatory; SI5332BD15705-GM1 offers superior jitter and broader frequency agility. |
Compared with Si5332AD15705-GM1, SI5332BD15705-GM1 trades embedded crystal convenience for external crystal control and lower bill-of-materials cost; versus LMK04832RHAR, it delivers lower jitter and finer frequency resolution but lacks JESD204B-specific features.
Availability
SI5332BD15705-GM1 is available at Aetrix Electronics and suitable for server motherboard design, 5G infrastructure development, and high-speed Ethernet switch production requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5332BD15705-GM1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.
The SI5332 family was designed to replace multiple fixed-frequency oscillators and clock buffers with a single, software-configurable timing device for high-performance computing, communications, and broadcast infrastructure.
FAQ
What is the maximum output frequency supported by the SI5332BD15705-GM1?
The SI5332BD15705-GM1 supports differential output frequencies up to 333.33 MHz and LVCMOS outputs up to 170 MHz. This range covers key standards including PCIe Gen1–6 (100/125/250/500 MHz), Ethernet (156.25/312.5/625 MHz), and CPRI/OBSAI (30.72/122.88/245.76 MHz), all with guaranteed 0 ppm synthesis error.
Does the SI5332BD15705-GM1 include an embedded crystal?
No, the SI5332BD15705-GM1 uses an external 16–50 MHz crystal connected to XA/XB pins. It belongs to the Si5332B grade (external crystal variant), unlike Si5332E/F/G/H/L grades which integrate a 50 MHz MEMS crystal. External crystal selection and PCB layout must follow Skyworks' low-jitter guidelines.
How many independent power supplies does the SI5332BD15705-GM1 support for its outputs?
The SI5332BD15705-GM1 provides six dedicated VDDO pins - one per differential output pair - enabling independent supply voltages (1.8 V, 2.5 V, or 3.3 V) for each output bank. This allows direct interfacing with mixed-voltage SoCs, FPGAs, and ASICs without external level-shifting circuitry.
Can the SI5332BD15705-GM1 generate PCIe Gen5/Gen6 reference clocks?
Yes, the SI5332BD15705-GM1 is explicitly qualified for PCIe Gen1 through Gen6 compliance, delivering <200 fs RMS phase jitter (190 fs typical with external crystal) and meeting all spectral, slew rate, and jitter accumulation requirements defined in PCI-SIG specifications for 100 MHz and 100 MHz ±300 ppm reference clocks.
Is I²C configuration required to operate the SI5332BD15705-GM1?
No - the SI5332BD15705-GM1 is factory-programmed with a ClockBuilder Pro-generated configuration stored in NVM. It powers up and delivers fully functional clocks immediately without host I²C interaction. I²C is optional for field reprogramming or dynamic profile switching during operation.
SI5332BD15705-GM1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Type:
- Clock Generator
- PLL:
- Yes
- Input:
- Clock, Crystal, LVCMOS
- Output:
- HCSL, LVCMOS, LVDS, LVPECL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:6
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 200MHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 1.71V ~ 3.63V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 32-QFN (5x5)
SI5332BD15705-GM1 FAQ
1.How can I place an order for SI5332BD15705-GM1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5332BD15705-GM1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5332BD15705-GM1 reliable?
The price and inventory of SI5332BD15705-GM1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332BD15705-GM1 is usually 5 days.
3.What payment methods are accepted for SI5332BD15705-GM1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332BD15705-GM1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5332BD15705-GM1?
SI5332BD15705-GM1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5332BD15705-GM1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5332BD15705-GM1?
For technical support, including SI5332BD15705-GM1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332BD15705-GM1 requirements.
6.How does Aetrix verify that SI5332BD15705-GM1 is sourced from the original manufacturer or authorized distributors?
All SI5332BD15705-GM1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332BD15705-GM1 meets industry standards.
7.What is the process for return or replacement of SI5332BD15705-GM1?
All SI5332BD15705-GM1 units undergo pre-shipment inspection (PSI). If there is an issue with SI5332BD15705-GM1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5332BD15705-GM1 part is unused and in its original packaging.
Return procedure for SI5332BD15705-GM1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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