Skyworks Solutions Inc. SI5332BD15706-GM1
- Part No.:
- SI5332BD15706-GM1
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
SI5332BD15706-GM1.pdf
- Description:
- LOW JITTER, 6-OUTPUT, ANY-FREQUE
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5332BD15706-GM1 from Skyworks is a 6-output, 32-pin programmable clock generator with MultiSynth™ fractional synthesis, delivering 190 fs RMS phase jitter (external crystal), 5–333.33 MHz differential output frequency range, and support for LVDS/LVPECL/HCSL/LVCMOS signal formats per output - used in PCIe Gen1–6 timing trees for servers and Ethernet switches.
For engineers reviewing the SI5332BD15706-GM1 datasheet, SI5332BD15706-GM1 pinout, SI5332BD15706-GM1 application, or SI5332BD15706-GM1 equivalent, key selection criteria include its 6-differential-output QFN package, external 16–50 MHz crystal interface, independent VDDO per output bank, I²C programmability, and PCIe SRIS compliance.
Technical Context
The SI5332BD15706-GM1 implements a wideband PLL paired with two independent MultiSynth fractional synthesis paths and five integer dividers, enabling simultaneous generation of non-integer-related frequencies across six differential outputs. Its cross-point mux routes any synthesized or reference source to any output path.
It operates in free-run mode using an external 16–50 MHz crystal on XA/XB pins or synchronous mode via CLKIN_2/CLKIN_2#, with initialization loading factory-programmed NVM configuration. Five universal hardware input pins support OE, spread-spectrum enable, or input selection - all defined in ClockBuilder Pro.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 6 differential clock outputs, each with dedicated VDDO supply pin |
| Phase jitter (RMS) | 190 fs - measured over 12 kHz–20 MHz offset, enables PCIe Gen5/6 compliance |
| Output frequency range | 5–333.33 MHz (differential); supports integer and fractional synthesis up to 250 MHz |
| Input reference | External crystal: 16–50 MHz on XA/XB; no embedded crystal (Si5332B grade) |
| Signal format per output | User-configurable LVDS, LVPECL, HCSL, or LVCMOS - set per-output via I²C or NVM |
| Supply voltages | VDD core: 1.8/2.5/3.3 V; VDDO outputs: 1.5/1.8/2.5/3.3 V - independent per bank |
| Interface | I²C serial interface (SCLK/SDATA) for runtime reconfiguration and NVM programming |
Pinout & Package
SI5332BD15706-GM1 uses a 32-pin, 5×5 mm QFN package (RoHS-6 compliant) with exposed thermal pad. Pin functions are validated per Skyworks Si5332 Family Reference Manual Section 6.3 (32-Pin Pin Descriptions).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA, XB | Crystal oscillator input | Connects to external 16–50 MHz fundamental-mode crystal; internal CL programmable (2.5–21.5 pF) |
| CLKIN_2, CLKIN_2# | Differential clock input | Accepts 10–250 MHz LVPECL/LVDS/HCSL; used for synchronous mode operation |
| OUT0–OUT5, OUT0b–OUT5b | Differential clock outputs | Six fully independent differential pairs; each configurable for LVDS/LVPECL/HCSL/LVCMOS |
| VDDO0–VDDO5 | Output driver supply | Individual 1.5/1.8/2.5/3.3 V supplies per output pair - enables mixed-voltage system interfacing |
| SCLK, SDATA | I²C interface | Standard two-wire bus for register access, configuration upload, and NVM programming |
| IN1–IN5 | Universal hardware inputs | Configurable as OE, spread-spectrum enable, input select, or I²C address - defined in ClockBuilder Pro |
Key Features
| Feature | Design Value |
|---|---|
| Any-frequency synthesis | Generates exact user-defined frequencies (e.g., 100.000 MHz, 156.25 MHz, 212.5 MHz) with 0 ppm error on all 6 outputs |
| Cross-point mux architecture | Routes any MultiSynth or integer divider output to any of the 6 differential outputs - enables flexible clock tree mapping |
| Independent output supply rails | VDDO0–VDDO5 allow each output pair to drive different voltage domains (e.g., 1.8 V FPGA + 3.3 V PHY) without level shifters |
| PCIe Gen1–6 & SRIS compliance | Meets jitter, slew rate, and spectral mask requirements for PCIe root complex, endpoint, and switch applications |
| Multi-profile NVM storage | Stores up to 16 configurations; enables fast, glitchless on-the-fly switching between preloaded timing profiles |
Applications
| Server CPU/Clock Tree | Ethernet Switch Timing |
|---|---|
Use Scenario: Generating synchronized clocks for CPU, memory controller, PCIe root complex, and onboard PHYs in dual-socket x86 servers. IC Role / Device Role / Timing Role: Primary clock generator providing 6 low-jitter differential clocks - including 100 MHz PCIe REFCLK, 133.33 MHz DDR, and 156.25 MHz Ethernet. Use Value: Replaces 4–5 discrete oscillators and fanout buffers; eliminates board-level skew and reduces BOM count by 60%. |
Use Scenario: Timing distribution across multi-port 10/25/100 GbE switch ASICs, SerDes lanes, and management processors. IC Role / Device Role / Timing Role: Centralized clock source delivering 156.25 MHz, 312.5 MHz, and 625 MHz clocks with sub-200 fs jitter to meet IEEE 802.3bj/ck jitter budgets. Use Value: Enables single-device compliance with SRIS (Spread Spectrum Independent Support) for multi-lane SerDes systems. |
| Small Cell Baseband Unit | Broadcast Video Processing |
Use Scenario: Synchronizing FPGA-based baseband processing, RFIC interfaces, and fronthaul transport (e.g., eCPRI) in 4G/5G small cells. IC Role / Device Role / Timing Role: Programmable clock hub generating 30.72 MHz LTE, 38.4 MHz 5G NR, and 122.88 MHz JESD204B clocks from one crystal reference. Use Value: Eliminates need for multiple fixed-frequency oscillators; allows field firmware updates to adapt to new air interface standards. |
Use Scenario: Driving SMPTE ST 2082 (12G-SDI), HDMI 2.1, and video processor clocks in broadcast cameras and production switchers. IC Role / Device Role / Timing Role: Low-phase-noise generator delivering 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks with <0.1° period jitter. Use Value: Prevents visible artifacts (jitter-induced shimmer) in uncompressed 4K/8K video pipelines; meets SMPTE RP184 jitter limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332AD15706-GM1 | Si5332A grade: supports both integer and fractional synthesis modes; same 6-output 32-QFN package and pinout | Required where non-integer ratios (e.g., 122.88 MHz from 25 MHz) must be generated with zero synthesis error | Select Si5332AD15706-GM1 if fractional synthesis is needed; SI5332BD15706-GM1 is integer-only per datasheet Table 2.1 |
| LMK04832RHAT | TI device: 14-output, JESD204B-compliant; higher power, larger 40-QFN package; no embedded crystal option | Better suited for high-channel-count JESD204B converter timing; lacks PCIe SRIS certification and multi-profile NVM | Choose LMK04832RHAT only when >6 outputs or deterministic latency for ADC/DAC sync are required - not a drop-in replacement |
Compared with SI5332BD15706-GM1, Si5332AD15706-GM1 adds fractional synthesis capability while retaining identical packaging and pin compatibility, whereas LMK04832RHAT offers higher output count at the cost of increased footprint, power, and loss of PCIe/SRIS qualification.
Availability
SI5332BD15706-GM1 is available at Aetrix Electronics and suitable for server motherboard design, Ethernet switch timing, and 5G small cell baseband applications requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.
Supply support for SI5332BD15706-GM1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.
The Si5332 family was designed to replace multiple fixed-frequency clocks and oscillators with a single, software-configurable, low-jitter timing IC for high-speed digital systems - targeting PCIe, Ethernet, and JESD204B infrastructure.
FAQ
What is the maximum differential output frequency supported by the SI5332BD15706-GM1?
The SI5332BD15706-GM1 supports differential output frequencies from 5 MHz to 333.33 MHz. This range covers standard rates including PCIe Gen1–6 REFCLK (100 MHz), Ethernet (156.25 MHz), and JESD204B (122.88 MHz, 245.76 MHz). The upper limit is constrained by the MultiSynth architecture and output driver bandwidth, not by the PLL itself.
Does the SI5332BD15706-GM1 include an embedded crystal?
No, the SI5332BD15706-GM1 does not include an embedded crystal. It belongs to the Si5332B grade, which requires an external 16–50 MHz fundamental-mode crystal connected to the XA/XB pins. Embedded crystal variants (e.g., Si5332E/F/G/H/L) use a factory-integrated 50 MHz MEMS resonator and carry different part number suffixes.
Can the SI5332BD15706-GM1 generate non-integer output frequencies like 122.88 MHz from a 25 MHz crystal?
No, the SI5332BD15706-GM1 is an integer-mode-only device per Skyworks' Ordering Guide (Figure 2.1). It cannot synthesize non-integer ratios such as 122.88 MHz from 25 MHz. For that capability, the Si5332A-grade part (e.g., Si5332AD15706-GM1) must be selected, as it supports both integer and fractional synthesis modes.
How many independent power supply rails does the SI5332BD15706-GM1 support for its outputs?
The SI5332BD15706-GM1 provides six independent VDDO supply pins (VDDO0 through VDDO5), one per differential output pair. Each can be set to 1.5 V, 1.8 V, 2.5 V, or 3.3 V, allowing direct interfacing with mixed-voltage devices (e.g., 1.8 V FPGA banks and 3.3 V PHYs) without external level shifters.
Is the SI5332BD15706-GM1 PCIe Gen5 and Gen6 compliant?
Yes, the SI5332BD15706-GM1 is explicitly listed as PCIe Gen1/2/3/4/5/6 and SRIS compliant in the Skyworks Si5332 Data Sheet Features List. Its 190 fs RMS phase jitter (12 kHz–20 MHz) meets the stringent jitter budget for PCIe Gen5 (≤2.0 ps RMS) and Gen6 (≤1.5 ps RMS) reference clocks when properly implemented with controlled impedance routing and termination.
SI5332BD15706-GM1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Type:
- Clock Generator
- PLL:
- Yes
- Input:
- Clock, Crystal, LVCMOS
- Output:
- HCSL, LVCMOS, LVDS, LVPECL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 2:6
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 200MHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 1.71V ~ 3.63V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 32-QFN (5x5)
SI5332BD15706-GM1 FAQ
1.How can I place an order for SI5332BD15706-GM1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5332BD15706-GM1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5332BD15706-GM1 reliable?
The price and inventory of SI5332BD15706-GM1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332BD15706-GM1 is usually 5 days.
3.What payment methods are accepted for SI5332BD15706-GM1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332BD15706-GM1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5332BD15706-GM1?
SI5332BD15706-GM1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5332BD15706-GM1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5332BD15706-GM1?
For technical support, including SI5332BD15706-GM1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332BD15706-GM1 requirements.
6.How does Aetrix verify that SI5332BD15706-GM1 is sourced from the original manufacturer or authorized distributors?
All SI5332BD15706-GM1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332BD15706-GM1 meets industry standards.
7.What is the process for return or replacement of SI5332BD15706-GM1?
All SI5332BD15706-GM1 units undergo pre-shipment inspection (PSI). If there is an issue with SI5332BD15706-GM1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5332BD15706-GM1 part is unused and in its original packaging.
Return procedure for SI5332BD15706-GM1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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