Skyworks Solutions Inc. SI5332C-D-AM2
- Part No.:
- SI5332C-D-AM2
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
SI5332C-D-AM2.pdf
- Description:
- IC CLOCK GENERATOR 40QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5332C-D-AM2 from Skyworks is an AEC-Q100 qualified automotive-grade clock generator delivering up to 8 differential outputs with 190 fs RMS phase jitter, PCIe Gen 1–5 compliance, and SmartClock™ health monitoring. It synthesizes any-frequency outputs from 5 to 333.33 MHz using MultiSynth™ fractional synthesis and supports mixed-supply operation across independent output banks - deployed in ADAS ECUs and digital cockpit systems.
For engineers reviewing the SI5332C-D-AM2 datasheet, SI5332C-D-AM2 pinout, SI5332C-D-AM2 application, or SI5332C-D-AM2 equivalent, key selection considerations include its 40-pin QFN package, dual fractional synthesis paths, configurable LVDS/LVPECL/HCSL/LVCMOS outputs, AEC-Q100 Grade 2 (−40°C to +105°C) qualification, and I²C-based field programming via ClockBuilder Pro™.
Technical Context
The SI5332C-D-AM2 implements a wideband PLL paired with two independent MultiSynth™ fractional synthesis paths and up to five integer dividers, enabling simultaneous generation of non-integer-related frequencies across eight differential outputs. Its architecture includes a cross-point mux for flexible frequency routing and universal hardware pins configurable for LOS, FOOF, or CLK_SEL functions.
SmartClock™ functionality monitors primary and redundant reference inputs (crystal or differential clock), reports loss-of-signal or out-of-frequency faults to a safety manager, and enables failover to backup sources. In full failure mode, AlwaysOn operation sustains outputs within ±5% of target frequency without external intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count | Up to 8 differential clock outputs (Si5332C variant supports integer+fractional synthesis mode) |
| Phase Jitter (RMS) | 190 fs over 12 kHz–20 MHz integration bandwidth - meets PCIe Gen5 jitter requirements |
| Frequency Range | Differential outputs: 5–333.33 MHz; supports non-integer ratios with zero ppm synthesis error |
| Input Support | External crystal (16–50 MHz) or differential clock (10–250 MHz); LVCMOS input up to 170 MHz |
| Supply Voltages | Core VDD: 1.8/2.5/3.3 V; independent VDDO banks support 1.5/1.8/2.5/3.3 V per output group |
| Operating Temp | AEC-Q100 Grade 2: −40°C to +105°C ambient - validated for under-hood automotive environments |
| Interface | I²C serial interface (up to 400 kHz) for runtime configuration and NVM programming |
Pinout & Package
SI5332C-D-AM2 is housed in a 6×6 mm, 40-pin QFN package with exposed thermal pad (RoHS-6 compliant, Pb-free). The package supports eight differential outputs, six VDDO supply pins, and seven user-configurable universal hardware pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OUT0 / OUT0b | Differential Output Pair | Bank A output; independently configurable signal format (LVDS/LVPECL/HCSL/LVCMOS) |
| VDDO0 | Output Supply | Provides dedicated 1.5/1.8/2.5/3.3 V supply for OUT0/OUT0b pair |
| OUT1 / OUT1b – OUT3 / OUT3b | Differential Output Pairs | Bank A outputs (OUT1–OUT3) share VDDO1; Bank B outputs (OUT4–OUT7) share VDDO2–VDDO5 |
| CLKIN_2 / CLKIN_2b | Differential Input | Primary reference input; accepts LVDS/LVPECL/HCSL signals from 10–250 MHz |
| XA / XB | Crytal Interface | Connects to 16–50 MHz fundamental-mode crystal; internal load capacitance programmable (2.5–21.5 pF) |
| SCLK / SDATA | I²C Interface | Standard bidirectional I²C bus (400 kHz max); used for register access and NVM programming |
| Universal1–Universal7 | Configurable HW Pin | Assigned in ClockBuilder Pro as LOS, FOOF, CLK_SEL, OE, RESET, or spread-spectrum enable |
Key Features
| Feature | Design Value |
|---|---|
| SmartClock™ Fault Monitoring | Real-time detection of input loss-of-signal or out-of-frequency faults; triggers system-level safety response via LOS/FOOF pins |
| AlwaysOn Mode | Continues clock output generation within ±5% frequency accuracy when both primary and redundant references fail |
| MultiSynth™ Synthesis | Two independent fractional synthesis paths enable concurrent generation of unrelated frequencies up to 250 MHz |
| Output Format Flexibility | Per-output selection among LVDS, LVPECL, HCSL, and LVCMOS - eliminates need for external level translators |
| Spread Spectrum | Programmable down or center spread (0.1–2.5% in 0.01% steps, 30–33 kHz) to reduce EMI in sensitive automotive modules |
Applications
| ADAS ECUs | Automotive Networking/Gateways |
|---|---|
Use Scenario: Synchronizing radar preprocessing units, vision processors, and sensor fusion SoCs in Level 2+ ADAS platforms. IC Role / Device Role / Timing Role: Central clock generator providing low-jitter, fault-monitored clocks to multiple high-speed interfaces (MIPI CSI-2, Gigabit Ethernet, CAN FD). Use Value: Replaces 3–4 discrete oscillators and clock buffers while meeting ASIL-B timing integrity requirements via SmartClock™ diagnostics. | Use Scenario: Timing backbone for vehicle domain controllers linking zonal ECUs, OTA update modules, and telematics units. IC Role / Device Role / Timing Role: Generates PCIe Gen4 reference clocks, Ethernet PHY clocks, and CAN FD bit clocks from single device with independent voltage domains. Use Value: Enables mixed-voltage operation (1.8 V MIPI, 3.3 V CAN FD) without level-shifting circuitry; reduces BOM count by 60% vs. legacy clock trees. |
| Digital Cockpit/IVI | Lidar/Radar Sensors |
Use Scenario: Driving infotainment SoCs, display controllers, and audio DSPs requiring precise multi-frequency clocking. IC Role / Device Role / Timing Role: Supplies synchronized 100 MHz PCIe, 200 MHz DDR, and 27 MHz HDMI TMDS clocks with sub-200 fs jitter. Use Value: Eliminates video artifacts and audio dropouts caused by clock domain misalignment; supports seamless UI rendering at 60 fps. | Use Scenario: Providing time-of-flight synchronization and ADC sampling clocks for 4D imaging radar and flash lidar modules. IC Role / Device Role / Timing Role: Delivers ultra-low-jitter (<200 fs) 1 GHz-equivalent sampling clocks derived from fractional synthesis paths. Use Value: Improves range resolution by >15% versus standard clock ICs; maintains timing accuracy across −40°C to +105°C operating range. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332B-D-AM2 | Same 40-pin QFN package and SmartClock™ features, but limited to 5–200 MHz output range and integer-only synthesis mode | Suitable for lower-frequency automotive gateways without PCIe Gen4/5 or high-speed SerDes requirements | Select when PCIe Gen3 or below suffices and fractional synthesis is unnecessary |
| Si5332D-D-AM2 | Identical package and pinout; supports only integer synthesis mode and 5–200 MHz outputs - no fractional path capability | Targeted at cost-sensitive ADAS camera modules where fixed-ratio clock trees suffice | Choose for simplified configuration and reduced ClockBuilder Pro setup complexity |
Compared with SI5332C-D-AM2, Si5332B-D-AM2 trades fractional synthesis flexibility for lower maximum frequency, while Si5332D-D-AM2 removes fractional capability entirely - making SI5332C-D-AM2 the only option supporting PCIe Gen5-compliant 333.33 MHz outputs with arbitrary frequency ratios.
Availability
SI5332C-D-AM2 is available at Aetrix Electronics and suitable for ADAS ECUs, automotive networking gateways, and digital cockpit systems requiring stable component supply, AEC-Q100 compliance, and long-term automotive lifecycle support.
Supply support for SI5332C-D-AM2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for automotive, infrastructure, and mobile markets.
The Si5332-AM family was designed specifically for automotive safety-critical timing applications, integrating SmartClock™ diagnostics, AEC-Q100 Grade 2 reliability, and multi-output flexibility to replace legacy clock trees in ADAS and automated driving systems.
FAQ
What is the maximum output frequency supported by SI5332C-D-AM2?
The SI5332C-D-AM2 supports differential output frequencies up to 333.33 MHz and LVCMOS outputs up to 170 MHz. This capability enables direct PCIe Gen5 reference clock generation and high-speed SerDes timing in automotive domain controllers. The 333.33 MHz limit applies specifically to the SI5332C variant, which uses integer+fractional synthesis mode - confirmed in Skyworks' Si5332-AM Ordering Guide and Electrical Specifications tables.
Does SI5332C-D-AM2 require an external crystal to operate?
No - SI5332C-D-AM2 can operate with either an external 16–50 MHz crystal connected to XA/XB pins or an external differential clock (10–250 MHz) applied to CLKIN_2/CLKIN_2# or CLKIN_3/CLKIN_3#. Crystal use is mandatory only in free-run mode; synchronous operation relies solely on the external clock input. Both modes are fully supported and selectable via ClockBuilder Pro configuration.
How many independent power domains does SI5332C-D-AM2 support for its outputs?
The SI5332C-D-AM2 supports six independent VDDO supply pins, enabling mixed-voltage operation across its eight differential outputs. Bank A (OUT0–OUT3) uses VDDO0–VDDO3; Bank B (OUT4–OUT7) uses VDDO4–VDDO5. Each VDDO pin accepts 1.5 V, 1.8 V, 2.5 V, or 3.3 V, allowing LVCMOS and differential outputs to coexist at different logic levels on the same device - critical for interfacing with heterogeneous SoCs in digital cockpits.
Can SI5332C-D-AM2 be reconfigured after power-up?
Yes - SI5332C-D-AM2 supports full in-system programming via its I²C interface (SCLK/SDATA). Engineers can dynamically adjust output frequencies, formats, and spread spectrum settings at runtime without resetting the device. ClockBuilder Pro Field Programmer also enables NVM reprogramming in the field. All configurations persist through power cycles when stored in NVM, and the device powers up in OTP-defined default mode if NVM is blank.
What fault detection capabilities does SmartClock™ provide in SI5332C-D-AM2?
SmartClock™ in SI5332C-D-AM2 continuously monitors primary and redundant reference inputs for loss-of-signal (LOS) and out-of-frequency (FOOF) faults. Detected faults are reported via dedicated universal hardware pins to a system safety manager or ASIL-rated MCU. Upon fault confirmation, external control logic can switch to the backup reference source. If both references fail, AlwaysOn mode maintains clock outputs within ±5% of nominal frequency - a deterministic behavior verified in Skyworks Application Note AN1292.
SI5332C-D-AM2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Clock Generator, Frequency Synthesizer
- PLL:
- Yes with Bypass
- Input:
- Clock, Crystal, LVCMOS
- Output:
- HCSL, LVCMOS, LVDS, LVPECL
- Number of Circuits:
- 2
- Ratio - Input:Output:
- 2:8
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 333.33MHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 1.71V ~ 3.46V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 40-QFN (6x6)
SI5332C-D-AM2 FAQ
1.How can I place an order for SI5332C-D-AM2 through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5332C-D-AM2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5332C-D-AM2 reliable?
The price and inventory of SI5332C-D-AM2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332C-D-AM2 is usually 5 days.
3.What payment methods are accepted for SI5332C-D-AM2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332C-D-AM2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5332C-D-AM2?
SI5332C-D-AM2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5332C-D-AM2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5332C-D-AM2?
For technical support, including SI5332C-D-AM2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332C-D-AM2 requirements.
6.How does Aetrix verify that SI5332C-D-AM2 is sourced from the original manufacturer or authorized distributors?
All SI5332C-D-AM2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332C-D-AM2 meets industry standards.
7.What is the process for return or replacement of SI5332C-D-AM2?
All SI5332C-D-AM2 units undergo pre-shipment inspection (PSI). If there is an issue with SI5332C-D-AM2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5332C-D-AM2 part is unused and in its original packaging.
Return procedure for SI5332C-D-AM2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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