Skyworks Solutions Inc. SI5332C-D-AM3R
- Part No.:
- SI5332C-D-AM3R
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
SI5332C-D-AM3R.pdf
- Description:
- IC CLOCK GENERATOR 48QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5332C-D-AM3R from Skyworks is an AEC-Q100 qualified automotive-grade clock generator with SmartClock™ health monitoring, delivering 190 fs RMS phase jitter and supporting up to 12 differential outputs (or 24 LVCMOS) across 5–333.33 MHz. It uses MultiSynth™ fractional synthesis for any-frequency generation with 0 ppm error and operates from –40 to +105 °C in ADAS ECUs and radar sensor systems.
For engineers reviewing the SI5332C-D-AM3R datasheet, SI5332C-D-AM3R pinout, SI5332C-D-AM3R application, or SI5332C-D-AM3R equivalent, key selection considerations include its 48-pin QFN package, dual-reference fault detection with AlwaysOn mode, PCIe Gen 1–5 compliance, per-output signal format configurability (LVDS/LVPECL/HCSL/LVCMOS), and factory-programmable NVM configuration via ClockBuilder Pro™.
Technical Context
The SI5332C-D-AM3R implements a wideband PLL paired with two independent MultiSynth™ fractional synthesis paths and up to five integer dividers, enabling simultaneous generation of non-integer-related frequencies on all 12 outputs. Its cross-point mux routes any synthesized or reference source to any output bank.
SmartClock™ functionality monitors primary and redundant reference inputs (crystal or differential clock), asserts LOS/FOOF signals on universal hardware pins, and enables automatic switchover to backup sources - with AlwaysOn mode sustaining ±5% frequency accuracy during dual-reference failure.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Jitter (RMS) | 190 fs - meets stringent timing budgets for PCIe Gen5 and high-speed SerDes interfaces |
| Output count | Up to 12 differential or 24 LVCMOS clocks - replaces multiple discrete oscillators and clock ICs in complex automotive SoC clock trees |
| Freq. synthesis | Any-frequency up to 333.33 MHz with 0 ppm error - eliminates need for custom crystal oscillators per frequency |
| Input range | Crystal: 16–50 MHz; Differential clock: 10–250 MHz; LVCMOS: 10–170 MHz - supports flexible reference sourcing |
| Temp. grade | AEC-Q100 Grade 2 (–40 to +105 °C) - validated for under-hood and cockpit ECU deployment |
| Compliance | PCIe Gen 1/2/3/4/5, SRIS, and common-clock mode - interoperable with automotive high-speed serial protocols |
| Supply voltages | VDD core: 1.8/2.5/3.3 V; VDDO banks: 1.5/1.8/2.5/3.3 V - enables mixed-voltage system clocking |
Pinout & Package
The SI5332C-D-AM3R is housed in a 7×7 mm, 48-pin QFN package (RoHS-6, Pb-free) with exposed thermal pad. Pin functions are defined per ClockBuilder Pro configuration; universal hardware pins support configurable roles including CLK_SEL, LOS, FOOF, OE, and RESET.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA/XB | Crystal input | Accepts 16–50 MHz fundamental-mode crystal for free-run operation; internal CL programmable (2.5–21.5 pF) |
| CLKIN_2/CLKIN_2#, CLKIN_3/CLKIN_3# | Differential reference inputs | Support LVPECL/LVDS/HCSL; enable synchronous locking and SmartClock™ dual-reference monitoring |
| OUT0–OUT11, OUT0b–OUT11b | Differential clock outputs | Configurable per-output signal format (LVDS/LVPECL/HCSL); grouped into four voltage-isolated banks (A–D) |
| VDDO0–VDDO5 | Output supply rails | Independent 1.5/1.8/2.5/3.3 V supplies per bank - enables mixed-signal SoC interface without level shifters |
| SCLK/SDATA | I²C interface | Standard 100/400 kHz I²C bus for runtime reconfiguration or NVM programming |
| Universal1–Universal7 | Configurable HW pins | Assigned in ClockBuilder Pro as LOS, FOOF, CLK_SEL[1:0], OE, RESET, or spread-spectrum enable |
Key Features
| Feature | Design Value |
|---|---|
| SmartClock™ fault detection | Monitors loss-of-signal and out-of-frequency faults on primary/redundant references; asserts dedicated pins for ASIL-B/C safety manager integration |
| AlwaysOn mode | Maintains clock outputs within ±5% frequency accuracy during total reference failure - critical for fail-operational ADAS subsystems |
| Per-output format control | Each of 12 differential outputs independently set to LVDS, LVPECL, HCSL, or LVCMOS - eliminates external level translators |
| Factory NVM programming | Custom configurations assigned unique part numbers in ClockBuilder Pro and programmed at wafer/test - zero runtime initialization overhead |
| Spread spectrum | Programmable down/center modulation (0.1–2.5% in 0.01% steps, 30–33 kHz) - reduces EMI in dense automotive PCB layouts |
Applications
| ADAS ECUs | Automotive Networking/Gateways |
|---|---|
Use Scenario: Centralized sensor fusion unit aggregating radar, camera, and ultrasonic data in Level 2+ autonomous driving systems. IC Role / Device Role / Timing Role: Primary clock generator synchronizing multi-domain SoCs (e.g., TI Jacinto, NXP S32G), PCIe switches, and GMSL serializers. Use Value: Replaces 4–6 discrete oscillators with single device; SmartClock™ enables ISO 26262 ASIL-B timing fault reporting to safety MCU. | Use Scenario: High-bandwidth vehicle gateway routing CAN FD, Ethernet AVB, and PCIe between domain controllers. IC Role / Device Role / Timing Role: Low-jitter clock source for Ethernet PHYs (100BASE-T1/1000BASE-T1), PCIe root complexes, and time-sensitive networking (TSN) controllers. Use Value: 190 fs jitter ensures <1 ns timing uncertainty across 10+ clock domains; PCIe Gen5 compliance supports future-proof bandwidth scaling. |
| Lidar/Radar Sensors | Digital Cockpit/IVI |
Use Scenario: Solid-state lidar module requiring precise time-of-flight synchronization across hundreds of VCSEL channels. IC Role / Device Role / Timing Role: Master clock distributor generating synchronized sampling clocks (e.g., 156.25 MHz, 312.5 MHz) for ADCs and FPGA-based beamformers. Use Value: Any-frequency synthesis eliminates custom crystals; differential outputs drive long traces with minimal skew (<10 ps inter-channel). | Use Scenario: Infotainment head unit integrating GPU, display controller, audio DSP, and USB 3.x peripherals. IC Role / Device Role / Timing Role: Multi-voltage clock hub supplying 1.8 V LVDS to MIPI D-PHY, 3.3 V LVCMOS to audio codecs, and 2.5 V LVPECL to HDMI transmitters. Use Value: Independent VDDO banks eliminate level-shifter ICs; spread spectrum reduces radiated emissions near AM/FM antennas. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332D-D-AM3R | Integer-mode only (no fractional synthesis); max 200 MHz output; same 48-QFN package and SmartClock™ features | Targeted at cost-sensitive applications where all required frequencies are integer multiples of reference (e.g., legacy Ethernet PHYs) | Select when PCIe Gen5 or arbitrary frequency synthesis is not required - lower NVM programming complexity and cost |
| Si5341-A01879-GM | Non-automotive grade (industrial temp); higher jitter (220 fs RMS); 10-output; no AEC-Q100 or SmartClock™ fault monitoring | Suitable for non-safety-critical infotainment or test equipment where automotive qualification is unnecessary | Choose only for non-automotive designs - lacks fault detection, AlwaysOn mode, and Grade 2 temperature validation |
Compared with SI5332C-D-AM3R, Si5332D-D-AM3R sacrifices fractional synthesis flexibility for reduced cost and simpler configuration, while Si5341-A01879-GM offers higher output count but omits automotive safety features and fails to meet AEC-Q100 requirements for ECU deployment.
Availability
SI5332C-D-AM3R is available at Aetrix Electronics and suitable for ADAS ECUs, automotive gateways, and radar/lidar sensor modules requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SI5332C-D-AM3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, automotive, and industrial markets.
The Si5332-AM family was designed specifically for automotive electronics requiring functional safety, high reliability, and flexible clock tree synthesis - targeting ADAS, digital cockpit, and vehicle networking applications.
FAQ
What is the maximum output frequency supported by the SI5332C-D-AM3R?
The SI5332C-D-AM3R supports differential output frequencies up to 333.33 MHz and LVCMOS outputs up to 170 MHz. This capability is enabled by its MultiSynth™ fractional synthesis architecture, which maintains 0 ppm frequency error across the full range. The SI5332C-D-AM3R achieves this while delivering 190 fs RMS phase jitter - making it suitable for PCIe Gen5 and high-speed SerDes applications where timing margin is critical.
Does the SI5332C-D-AM3R support AEC-Q100 qualification?
Yes, the SI5332C-D-AM3R is fully AEC-Q100 qualified for Grade 2 (–40 to +105 °C) operation and also meets AEC-Q006 for robustness against board-level stress. This qualification covers the entire device - including internal PLL, MultiSynth™ synthesizers, SmartClock™ monitoring logic, and I²C interface - ensuring reliability in automotive under-hood and cockpit environments where thermal cycling and vibration are present.
How does SmartClock™ fault detection work on the SI5332C-D-AM3R?
SmartClock™ on the SI5332C-D-AM3R continuously monitors both primary and redundant reference inputs (crystal or differential clocks) for loss-of-signal (LOS) and out-of-frequency (FOOF) faults. When triggered, it asserts dedicated universal hardware pins (configurable in ClockBuilder Pro) to notify a system safety manager. With external control, the SI5332C-D-AM3R can switch to the backup reference; if both fail, AlwaysOn mode sustains outputs within ±5% frequency accuracy.
Can the SI5332C-D-AM3R generate different signal formats on individual outputs?
Yes, the SI5332C-D-AM3R allows per-output signal format selection - each of its 12 differential outputs can be independently configured as LVDS, LVPECL, HCSL, or LVCMOS via ClockBuilder Pro or I²C register writes. This eliminates the need for external level translators and supports heterogeneous SoC interfaces (e.g., LVDS for MIPI, LVPECL for Ethernet PHYs, LVCMOS for microcontrollers) from a single clock source.
Is factory programming available for the SI5332C-D-AM3R?
Yes, Skyworks provides free factory NVM programming for the SI5332C-D-AM3R using ClockBuilder Pro™. Users define their exact frequency plan, output formats, and SmartClock™ pin assignments in the software, which generates a unique custom part number (e.g., SI5332C-D-AM3R). Devices ordered with that part number ship preprogrammed - eliminating runtime initialization and ensuring deterministic power-up behavior in automotive ECUs.
SI5332C-D-AM3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Clock Generator, Frequency Synthesizer
- PLL:
- Yes with Bypass
- Input:
- Clock, Crystal, LVCMOS
- Output:
- HCSL, LVCMOS, LVDS, LVPECL
- Number of Circuits:
- 2
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 333.33MHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 1.71V ~ 3.46V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 48-QFN (6x6)
SI5332C-D-AM3R FAQ
1.How can I place an order for SI5332C-D-AM3R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5332C-D-AM3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5332C-D-AM3R reliable?
The price and inventory of SI5332C-D-AM3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332C-D-AM3R is usually 5 days.
3.What payment methods are accepted for SI5332C-D-AM3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332C-D-AM3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5332C-D-AM3R?
SI5332C-D-AM3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5332C-D-AM3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5332C-D-AM3R?
For technical support, including SI5332C-D-AM3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332C-D-AM3R requirements.
6.How does Aetrix verify that SI5332C-D-AM3R is sourced from the original manufacturer or authorized distributors?
All SI5332C-D-AM3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332C-D-AM3R meets industry standards.
7.What is the process for return or replacement of SI5332C-D-AM3R?
All SI5332C-D-AM3R units undergo pre-shipment inspection (PSI). If there is an issue with SI5332C-D-AM3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5332C-D-AM3R part is unused and in its original packaging.
Return procedure for SI5332C-D-AM3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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