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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5332DC09563-GM2R

Name: SI5332DC09563-GM2R
Brand: Skyworks Solutions Inc.
SKU: SI5332DC09563-GM2R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5332DC09563-GM2R

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: SI5332DC09563-GM2R.pdf

Description:: IC CLOCK GENERATOR QFN

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Product details

Overview

SI5332DC09563-GM2R from Silicon Labs is an 8-output, factory-programmed, low-jitter clock generator based on MultiSynth™ fractional synthesis. It delivers up to 333.33 MHz differential outputs with 190 fs RMS phase jitter (external crystal), supports LVDS/LVPECL/HCSL/LVCMOS per-output formatting, and operates across –40 to +85 °C for Ethernet switch timing and PCIe Gen4 reference clocking.

For engineers reviewing the SI5332DC09563-GM2R datasheet, SI5332DC09563-GM2R pinout, SI5332DC09563-GM2R application, or SI5332DC09563-GM2R equivalent, key selection criteria include output count (8), package (40-pin QFN), embedded vs. external crystal configuration, I²C programmability, and multi-bank VDDO voltage support for mixed-supply clock trees.

Technical Context

The SI5332DC09563-GM2R implements a two-stage synthesis architecture: a wideband PLL locks to either an external 16–50 MHz crystal or differential input clock (10–250 MHz), then feeds up to three independent MultiSynth fractional dividers and five integer dividers. Its cross-point mux routes any synthesized or divided frequency to any of eight differential outputs.

Each output bank (Bank A/B) shares a dedicated VDDO supply (1.8/2.5/3.3 V), enabling simultaneous LVDS and LVPECL signaling. The device supports glitchless on-the-fly frequency changes via multi-profile NVM storage (up to 16 configurations), and configurable skew (±122.5 ps in 35 ps steps) per differential pair.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	8 differential clock outputs (supports up to 16 LVCMOS via dual-pin mode)
Phase Jitter (RMS)	190 fs - meets PCIe Gen4 SRIS and Ethernet 10G/25G jitter budgets
Max Output Frequency	333.33 MHz differential - enables direct generation of 100G KR4 reference clocks
Input Reference	External crystal (16–50 MHz) - no embedded crystal; requires XA/XB connection
Output Signal Formats	Per-output LVDS, LVPECL, HCSL, or LVCMOS - eliminates need for external level translators
VDDO Flexibility	Independent 1.8 V / 2.5 V / 3.3 V supplies per bank - supports mixed-voltage SerDes interfaces
Control Interface	I²C (400 kHz standard mode) - enables host MCU-based dynamic reconfiguration

Pinout & Package

SI5332DC09563-GM2R uses a 40-pin QFN (6 × 6 mm, 0.5 mm pitch) RoHS-6-compliant package with exposed thermal pad. Pin functions are defined per ClockBuilder Pro configuration; default hardware inputs include CLKIN_SEL[1:0], OEb, and SS_EN.

Pin/Terminal	Circuit Role	Design Meaning
XA/XB	Crystal Oscillator Input	Connects external 16–50 MHz fundamental-mode crystal; internal CL selectable (2–30 pF)
CLKIN_2/CLKIN_2#	Differential Reference Input	Accepts LVDS/LVPECL/HCSL (10–250 MHz); AC-coupled; used for synchronous mode
OUT0–OUT7	Differential Clock Outputs	Configurable per-output format; Bank A (OUT0–OUT3) and Bank B (OUT4–OUT7) share VDDO1/VDDO2
VDDO0–VDDO5	Output Supply Rails	VDDO0/VDDO1 power Bank A; VDDO2/VDDO3 power Bank B; VDDO4/VDDO5 reserved for future expansion
SCLK/SDATA	I²C Serial Interface	Standard bidirectional I²C bus (400 kHz); supports in-system programming and runtime updates
OEb	Output Enable (Active Low)	Hardware-controlled global enable/disable; prevents runt pulses via synchronous disable logic

Key Features

Feature	Design Value
MultiSynth™ Fractional Synthesis	Enables any-frequency output (5–333.33 MHz) with 0 ppm synthesis error - replaces multiple fixed-frequency oscillators
Per-Output Format Selection	LVDS/LVPECL/HCSL/LVCMOS configurable independently - eliminates external signal conditioning ICs
Multi-Bank VDDO Architecture	Two independent output banks with separate 1.8/2.5/3.3 V supplies - supports heterogeneous SerDes voltage domains
Configurable Output Skew	±122.5 ps adjustment in 35 ps steps per differential pair - enables precise timing alignment in parallel interfaces
Multi-Profile NVM Storage	Stores up to 16 complete clock configurations - allows fast switching between system operating modes (e.g., sleep/active)

Applications

100G Ethernet Switch Timing	PCIe Gen4 Server Reference Clock
Use Scenario: High-density data center switch ASICs requiring synchronized 100G KR4 lanes with strict jitter compliance. IC Role / Device Role / Timing Role: Primary clock generator delivering eight 100.0125 MHz differential clocks with <200 fs RMS jitter to SerDes PHYs. Use Value: Eliminates discrete oscillator array; reduces board area by 40% and jitter accumulation across lanes.	Use Scenario: Dual-CPU server motherboard needing compliant PCIe Gen4 reference clocks for CPU, PCH, and add-in cards. IC Role / Device Role / Timing Role: Centralized clock source generating 100 MHz LVDS and 100 MHz LVPECL outputs with SRIS compliance. Use Value: Meets PCIe Gen4 ±300 fs total jitter spec at receiver; avoids costly board-level jitter cleanup circuits.
5G Small Cell Baseband Timing	Industrial Embedded Computing Clock Tree
Use Scenario: Compact 5G small cell unit requiring synchronized fronthaul (eCPRI) and backhaul (CPRI) interfaces. IC Role / Device Role / Timing Role: Single-device clock tree generating 245.76 MHz (eCPRI), 30.72 MHz (CPRI), and 10 MHz (sync) outputs. Use Value: Supports hitless frequency switching between TDD/FDD modes via stored profiles; reduces BOM count by 7 parts.	Use Scenario: Ruggedized industrial controller with mixed-voltage peripherals (FPGA, ADC, Ethernet PHY). IC Role / Device Role / Timing Role: Configurable clock hub providing 125 MHz LVDS (FPGA), 50 MHz LVCMOS (ADC), and 25 MHz HCSL (PHY). Use Value: Independent VDDO rails allow 3.3 V HCSL and 1.8 V LVDS simultaneously; simplifies power domain isolation.

100G Ethernet Switch Timing

PCIe Gen4 Server Reference Clock

Use Scenario: High-density data center switch ASICs requiring synchronized 100G KR4 lanes with strict jitter compliance.

IC Role / Device Role / Timing Role: Primary clock generator delivering eight 100.0125 MHz differential clocks with <200 fs RMS jitter to SerDes PHYs.

Use Value: Eliminates discrete oscillator array; reduces board area by 40% and jitter accumulation across lanes.

Use Scenario: Dual-CPU server motherboard needing compliant PCIe Gen4 reference clocks for CPU, PCH, and add-in cards.

IC Role / Device Role / Timing Role: Centralized clock source generating 100 MHz LVDS and 100 MHz LVPECL outputs with SRIS compliance.

Use Value: Meets PCIe Gen4 ±300 fs total jitter spec at receiver; avoids costly board-level jitter cleanup circuits.

5G Small Cell Baseband Timing

Industrial Embedded Computing Clock Tree

Use Scenario: Compact 5G small cell unit requiring synchronized fronthaul (eCPRI) and backhaul (CPRI) interfaces.

IC Role / Device Role / Timing Role: Single-device clock tree generating 245.76 MHz (eCPRI), 30.72 MHz (CPRI), and 10 MHz (sync) outputs.

Use Value: Supports hitless frequency switching between TDD/FDD modes via stored profiles; reduces BOM count by 7 parts.

Use Scenario: Ruggedized industrial controller with mixed-voltage peripherals (FPGA, ADC, Ethernet PHY).

IC Role / Device Role / Timing Role: Configurable clock hub providing 125 MHz LVDS (FPGA), 50 MHz LVCMOS (ADC), and 25 MHz HCSL (PHY).

Use Value: Independent VDDO rails allow 3.3 V HCSL and 1.8 V LVDS simultaneously; simplifies power domain isolation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332DC09562-GM2R	Same 40-pin QFN package and 8-output architecture, but configured for embedded 50 MHz crystal (E-grade)	Eliminates external crystal placement and layout; higher cost; reduced design flexibility for input reference sourcing	Select when board space is constrained and crystal layout complexity must be avoided
Si5341-A01871-GM	12-output variant in 48-QFN; higher integration (integrated LDOs); 175 fs jitter (embedded crystal)	Supports larger clock trees; requires PCB redesign for 48-pin footprint and additional decoupling	Select when >8 outputs are needed or ultra-low jitter (<180 fs) is mandatory for optical transport applications

Compared with SI5332DC09563-GM2R, Si5332DC09562-GM2R trades external crystal flexibility for simplified layout, while Si5341-A01871-GM adds output count and jitter performance at the cost of footprint and power delivery complexity.

Availability

SI5332DC09563-GM2R is available at Aetrix Electronics and suitable for Ethernet switches, PCIe Gen4 servers, and 5G small cell baseband systems requiring stable component supply, long-term lifecycle assurance, and factory-programmed precision timing.

Supply support for SI5332DC09563-GM2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Silicon Labs is a fabless semiconductor company specializing in timing, wireless, and IoT solutions, with over 20 years of leadership in high-performance clock technology.

The Si5332 family was designed to replace multiple discrete clock sources in high-speed digital systems, targeting applications demanding low jitter, flexible frequency synthesis, and mixed-signal compatibility across datacenter, telecom, and industrial markets.

FAQ

What is the crystal requirement for SI5332DC09563-GM2R?

The SI5332DC09563-GM2R requires an external fundamental-mode crystal connected to XA/XB pins, operating between 16 MHz and 50 MHz. It does not include an embedded crystal; the "D" in the part number denotes external crystal configuration. Load capacitance is programmable from 2 pF to 30 pF via register settings, and external capacitors may be added if needed.

Does SI5332DC09563-GM2R support spread spectrum clocking?

Yes, SI5332DC09563-GM2R supports both center-spread and down-spread spectrum modulation from –0.1% to –2.5% in 0.01% increments at 30–33 kHz. Spread spectrum can be enabled via I²C register write or by assigning a universal hardware input pin (e.g., SS_EN) in ClockBuilder Pro, helping reduce EMI in dense PCB layouts.

How many independent voltage domains does SI5332DC09563-GM2R support for its outputs?

SI5332DC09563-GM2R supports two independent output voltage domains: Bank A (OUT0–OUT3) powered by VDDO0/VDDO1 and Bank B (OUT4–OUT7) powered by VDDO2/VDDO3. Each domain accepts 1.8 V, 2.5 V, or 3.3 V, enabling concurrent LVDS (2.5 V) and LVPECL (3.3 V) signaling without level-shifting components.

Can SI5332DC09563-GM2R generate non-integer output frequencies?

Yes, SI5332DC09563-GM2R uses MultiSynth™ fractional synthesis to generate any output frequency from 5 MHz to 333.33 MHz with zero ppm error - including non-integer ratios like 122.88 MHz or 245.76 MHz required for eCPRI and CPRI interfaces. This capability is confirmed in the Si5332 datasheet Section 3.3 and ClockBuilder Pro configuration flow.

Is SI5332DC09563-GM2R pin-compatible with other Si5332 variants in the 40-pin QFN package?

Yes, all Si5332-GM2R variants (e.g., SI5332DC09562-GM2R, SI5332DC09564-GM2R) share identical 40-pin QFN mechanical and electrical pinouts. Differences lie only in factory-programmed NVM content (crystal type, output frequencies, formats), not in pin function mapping or package dimensions - enabling drop-in replacement within the same GM2R footprint.

SI5332DC09563-GM2R Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tape & Reel (TR)

Product Status:: Not For New Designs

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5332DC09563-GM2R FAQ

1.How can I place an order for SI5332DC09563-GM2R through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5332DC09563-GM2R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5332DC09563-GM2R reliable?

The price and inventory of SI5332DC09563-GM2R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332DC09563-GM2R is usually 5 days.

3.What payment methods are accepted for SI5332DC09563-GM2R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332DC09563-GM2R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5332DC09563-GM2R?

SI5332DC09563-GM2R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5332DC09563-GM2R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5332DC09563-GM2R?

For technical support, including SI5332DC09563-GM2R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332DC09563-GM2R requirements.

6.How does Aetrix verify that SI5332DC09563-GM2R is sourced from the original manufacturer or authorized distributors?

All SI5332DC09563-GM2R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332DC09563-GM2R meets industry standards.

7.What is the process for return or replacement of SI5332DC09563-GM2R?

All SI5332DC09563-GM2R units undergo pre-shipment inspection (PSI). If there is an issue with SI5332DC09563-GM2R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5332DC09563-GM2R part is unused and in its original packaging.

Return procedure for SI5332DC09563-GM2R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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