My Inquiry
My Account
Skyworks Solutions Inc. SI5332D-D-AM3R
- Part No.:
- SI5332D-D-AM3R
- Manufacturer:
- Skyworks Solutions Inc.
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
SI5332D-D-AM3R.pdf
- Description:
- IC CLOCK GENERATOR 48QFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,180
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SI5332D-D-AM3R from Skyworks is an AEC-Q100 Grade 2 automotive clock generator delivering up to 12 differential outputs with 190 fs RMS phase jitter, integer/fractional synthesis up to 200 MHz output frequency, and SmartClock™ health monitoring for dual-reference fault detection and failover. It serves as a single-chip clock tree solution in ADAS ECUs and radar sensor modules.
For engineers reviewing the SI5332D-D-AM3R datasheet, SI5332D-D-AM3R pinout, SI5332D-D-AM3R application, or SI5332D-D-AM3R equivalent, key selection criteria include its 48-pin QFN package, 12-output capability, ±5% AlwaysOn mode fallback, PCIe Gen 1–5 compliance, and I²C programmability via ClockBuilder Pro™.
Technical Context
The SI5332D-D-AM3R implements a two-stage synthesis architecture: a wideband PLL locks to 16–50 MHz crystal or 10–250 MHz differential/LVCMOS reference, then feeds two independent MultiSynth fractional synthesizers and five integer dividers. Its cross-point mux routes any synthesized or divided frequency to any output bank.
Each of four output banks (A–D) shares a dedicated VDDO supply (1.5/1.8/2.5/3.3 V), enabling mixed-voltage operation. SmartClock™ leverages universal hardware pins (e.g., LOS, FOOF, CLK_SEL) to monitor input health, signal faults to safety MCUs, and enable external-controlled switchover to redundant references - with AlwaysOn mode sustaining clocks within ±5% on total reference loss.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count | 12 differential outputs (Si5332D variant supports up to 200 MHz; not 333.33 MHz) |
| Phase jitter (RMS) | 190 fs - enables PCIe Gen5 and high-speed SerDes timing margin |
| Input range | Crystal: 16–50 MHz; Differential clock: 10–250 MHz; LVCMOS: 10–170 MHz |
| Output range | Differential: 5–200 MHz; LVCMOS: 5–170 MHz - matches Si5332D specification tier |
| Supply voltages | VDD core: 1.8/2.5/3.3 V; VDDO per bank: 1.5/1.8/2.5/3.3 V - supports mixed-signal SoC interfaces |
| Compliance | AEC-Q100 Grade 2 (−40 °C to +105 °C); RoHS-6; PCIe Gen1/2/3/4/5 common clock & SRIS |
| Interface | I²C serial interface (SCLK/SDATA) - enables runtime reconfiguration and NVM programming |
Pinout & Package
The SI5332D-D-AM3R is housed in a 7×7 mm, 48-pin QFN package (Moisture Sensitivity Level 3, Pb-free, RoHS-6 compliant) with exposed thermal pad. Pin functions are defined per ClockBuilder Pro configuration; universal hardware pins support configurable roles including LOS, FOOF, CLK_SEL, OE, and RESET.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| XA/XB | Crystal oscillator input | Accepts 16–50 MHz fundamental-mode crystal; internal CL tuning (2.5–21.5 pF) minimizes external components |
| CLKIN_2/CLKIN_2#, CLKIN_3/CLKIN_3# | Differential reference inputs | Support LVPECL/LVDS/HCSL; selectable as primary/redundant sources for SmartClock™ fault detection |
| OUT0–OUT11, OUT0b–OUT11b | Differential clock outputs | 12 fully independent pairs; each configurable for LVDS/LVPECL/HCSL; per-bank VDDO enables mixed-voltage routing |
| VDDO0–VDDO5 | Output bank supply rails | Six dedicated VDDO pins power four output banks (A–D); allow 1.5/1.8/2.5/3.3 V per bank for heterogeneous SoC interfacing |
| Universal1–Universal7 | Configurable hardware control pins | Assigned in ClockBuilder Pro as LOS (loss-of-signal), FOOF (frequency-out-of-fault), CLK_SEL, OE, or RESET - no fixed function |
| SCLK/SDATA | I²C interface | Standard two-wire bus for register access, NVM programming, and dynamic frequency updates at power-up |
Key Features
| Feature | Design Value |
|---|---|
| SmartClock™ health monitoring | Real-time detection of input loss-of-signal and out-of-frequency faults; triggers system-level safety response via LOS/FOOF pins |
| AlwaysOn mode | Maintains all 12 outputs within ±5% of target frequency during complete reference failure - critical for ASIL-B/C systems |
| MultiSynth™ fractional synthesis | Two independent fractional paths enable simultaneous non-integer ratios (e.g., 100 MHz + 125.0001 MHz) without external VCXOs |
| Per-bank VDDO flexibility | Four output banks powered independently - eliminates level-shifters when driving 1.8 V SerDes, 3.3 V MCU, and 2.5 V PHY on same board |
| PCIe Gen1–5 compliance | Meets jitter, skew, and spread-spectrum requirements for root complex, endpoint, and switch applications without add-on filtering |
Applications
| ADAS ECU Clocking | Automotive Radar Sensor Timing |
|---|---|
Use Scenario: Centralized timing for multi-core processor, CAN FD gateway, and Gigabit Ethernet PHY in front-camera ECU. IC Role / Device Role / Timing Role: Single-chip clock generator replacing discrete oscillators and fanout buffers; provides synchronized 100 MHz processor clock, 40 MHz CAN FD, and 125 MHz Ethernet reference. Use Value: Reduces BOM count by 4+ components; eliminates inter-clock skew; AEC-Q100 qualification ensures reliability across thermal cycles. | Use Scenario: High-precision timing for 77 GHz FMCW radar transceiver with ADC sampling and DSP clocking. IC Role / Device Role / Timing Role: Generates low-jitter 122.88 MHz ADC sampling clock and 150 MHz DSP core clock from single crystal reference. Use Value: 190 fs RMS jitter preserves ENOB in 14-bit ADC; fractional synthesis avoids spurs from integer-only dividers. |
| Digital Cockpit SoC Interface | Lidar System Synchronization |
Use Scenario: Driving display controller, audio codec, and video decoder in infotainment head unit with mixed-voltage interfaces. IC Role / Device Role / Timing Role: Supplies 148.5 MHz HDMI TMDS, 44.1 kHz audio MCLK, and 200 MHz GPU clock - each on separate VDDO banks. Use Value: Eliminates need for three separate voltage-rail clock ICs; per-output format configurability (LVDS/HCSL/LVCMOS) matches native SoC I/O standards. | Use Scenario: Time-of-flight synchronization across multiple 905 nm pulsed laser channels and SPAD arrays in solid-state lidar. IC Role / Device Role / Timing Role: Distributes phase-aligned 100 MHz timebase to laser driver, TDC, and FPGA with sub-10 ps inter-channel skew. Use Value: Cross-point mux and per-output delay adjustment enable deterministic skew calibration; SmartClock™ monitors master oscillator for functional safety compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332D-D-AM2R | 40-pin QFN, max 8 differential outputs; identical jitter, synthesis, and SmartClock™ features | Lower pin count and output count - suitable for gateway ECUs with ≤8 clock domains | Select when system requires fewer outputs and smaller PCB footprint; shares same ClockBuilder Pro configuration flow |
| Si5341-A01869-GM | Non-automotive, 12-output, 150 fs jitter; lacks AEC-Q100, SmartClock™, and AlwaysOn mode | Targeted at industrial/test equipment - no fault monitoring or automotive temperature grade | Consider only for non-safety-critical designs where ultra-low jitter outweighs functional safety requirements |
Compared with SI5332D-D-AM3R, the AM2R reduces output count and package size while retaining full automotive qualification and SmartClock™; the Si5341 offers lower jitter but omits fault resilience features essential for ASIL-compliant systems.
Availability
SI5332D-D-AM3R is available at Aetrix Electronics and suitable for ADAS ECUs, automotive radar sensors, and digital cockpit systems requiring stable component supply, long-term automotive lifecycle support, and AEC-Q100-compliant timing solutions.
Supply support for SI5332D-D-AM3R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for automotive, infrastructure, and mobile markets.
The Si5332-AM family was designed specifically for automotive ADAS, radar, and infotainment systems requiring AEC-Q100 qualification, functional safety-aware clock monitoring, and flexible multi-output synthesis in harsh environments.
FAQ
What is the maximum output frequency supported by SI5332D-D-AM3R?
The SI5332D-D-AM3R supports differential output frequencies up to 200 MHz - consistent with the Si5332D variant designation in Skyworks' ordering guide. This differs from Si5332A/C variants (333.33 MHz). The 200 MHz limit applies regardless of synthesis mode (integer or fractional) and is validated across the full −40 °C to +105 °C operating range.
Does SI5332D-D-AM3R require external loop filter components?
No, SI5332D-D-AM3R integrates a fully monolithic PLL with no external loop filter components required. Its wideband PLL uses internal charge pump and filter circuitry, simplifying PCB layout and eliminating tuning variables. This integration contributes to the device's 190 fs RMS jitter performance and AEC-Q100 qualification robustness.
How does SmartClock™ fault detection work on SI5332D-D-AM3R?
SmartClock™ on SI5332D-D-AM3R monitors primary and redundant reference inputs for loss-of-signal (LOS) and frequency-out-of-fault (FOOF). When triggered, it asserts dedicated universal hardware pins (configurable in ClockBuilder Pro) to alert a safety MCU. External logic can then switch to the backup reference - and if both fail, SI5332D-D-AM3R enters AlwaysOn mode, sustaining outputs within ±5% of target frequency.
Can SI5332D-D-AM3R generate both LVDS and LVPECL outputs simultaneously?
Yes, SI5332D-D-AM3R supports per-output signal format configuration: each of the 12 differential outputs can be independently set to LVDS, LVPECL, HCSL, or LVCMOS via ClockBuilder Pro or I²C registers. This allows concurrent LVDS (e.g., for FPGA) and LVPECL (e.g., for SerDes) outputs without external level shifters or additional clock ICs.
Is factory programming included for custom SI5332D-D-AM3R configurations?
Yes, custom SI5332D-D-AM3R configurations generated in ClockBuilder Pro receive unique part numbers (e.g., SI5332D-D-AM3R-XXXXX) and are factory-programmed into NVM at no additional cost. This eliminates field programming steps, ensures first-power-up readiness, and guarantees configuration integrity across automotive production volumes.
SI5332D-D-AM3R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- MultiSynth™
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Clock Generator, Frequency Synthesizer
- PLL:
- Yes with Bypass
- Input:
- Clock, Crystal, LVCMOS
- Output:
- HCSL, LVCMOS, LVDS, LVPECL
- Number of Circuits:
- 2
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 333.33MHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 1.71V ~ 3.46V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 48-QFN (6x6)
SI5332D-D-AM3R FAQ
1.How can I place an order for SI5332D-D-AM3R through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5332D-D-AM3R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5332D-D-AM3R reliable?
The price and inventory of SI5332D-D-AM3R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332D-D-AM3R is usually 5 days.
3.What payment methods are accepted for SI5332D-D-AM3R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332D-D-AM3R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5332D-D-AM3R?
SI5332D-D-AM3R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5332D-D-AM3R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5332D-D-AM3R?
For technical support, including SI5332D-D-AM3R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332D-D-AM3R requirements.
6.How does Aetrix verify that SI5332D-D-AM3R is sourced from the original manufacturer or authorized distributors?
All SI5332D-D-AM3R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332D-D-AM3R meets industry standards.
7.What is the process for return or replacement of SI5332D-D-AM3R?
All SI5332D-D-AM3R units undergo pre-shipment inspection (PSI). If there is an issue with SI5332D-D-AM3R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5332D-D-AM3R part is unused and in its original packaging.
Return procedure for SI5332D-D-AM3R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SI5332D-D-AM3R Tags
-
CD74HCT4046AM96
Texas Instruments
-
MC14046BDWR2G
onsemi
-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments
-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.
-
CY2305SXI-1T
Infineon Technologies
-
570BILFT
Renesas
-
CDCE913PWR
Texas Instruments
-
CY2305SXI-1HT
Infineon Technologies
-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
