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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5332D-D-GM2R

Name: SI5332D-D-GM2R
Brand: Skyworks Solutions Inc.
SKU: SI5332D-D-GM2R
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5332D-D-GM2R

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 40-VFQFN Exposed Pad

Datasheet:: SI5332D-D-GM2R.pdf

Description:: IC CLOCK GENERATOR 40QFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5332D-D-GM2R from Skyworks is an 8-output, externally crystal-referenced programmable clock generator supporting integer and fractional synthesis up to 200 MHz output frequency, 190 fs RMS phase jitter, PCIe Gen1–6 compliance, and user-configurable LVDS/LVPECL/HCSL/LVCMOS signal formats per output.

For engineers reviewing the SI5332D-D-GM2R datasheet, SI5332D-D-GM2R pinout, SI5332D-D-GM2R application, or SI5332D-D-GM2R equivalent, key selection considerations include its 40-pin QFN package, dual MultiSynth fractional synthesis paths, independent VDDO banks for mixed-supply clock distribution, I²C programmability, and factory preprogramming via ClockBuilder Pro for application-specific configurations.

Technical Context

The SI5332D-D-GM2R implements a wideband PLL locked to a 16–50 MHz external crystal (XA/XB), feeding two independent MultiSynth fractional synthesis paths and five integer dividers. Its cross-point multiplexer routes any synthesized or divided clock to any of eight differential outputs.

Each output bank supports independent supply voltages (1.8/2.5/3.3 V for differential; 1.5/1.8/2.5/3.3 V for LVCMOS), configurable skew, synchronous disable, and spread spectrum (0.1–2.5% down/center at 30–33 kHz). Input selection is register- or hardware-pin controlled, with no hitless switching between inputs differing by >±1000 ppm.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	8 differential clock outputs (Si5332D variant in 40-pin QFN)
Max output frequency	200 MHz - defines upper limit for PCIe Gen4/5 reference clocks and high-speed SerDes timing
Phase jitter (RMS)	190 fs - measured over 12 kHz–20 MHz offset, enabling compliance with PCIe Gen5/6 and SRIS specs
Input reference	External crystal (16–50 MHz) - requires no embedded oscillator; enables low-cost, flexible free-run operation
Synthesis modes	Integer and fractional - supports non-integer ratios (e.g., 156.25 MHz → 100.01 MHz) without external components
Output formats	LVDS, LVPECL, HCSL, LVCMOS - per-output configurability eliminates need for level-shifting buffers
Supply voltage (core)	1.8/2.5/3.3 V VDD - decoupled from output supplies, simplifying power domain partitioning
Operating temperature	–40 to +85 °C - qualified for industrial and telecom infrastructure environments

Pinout & Package

SI5332D-D-GM2R is housed in a 6×6 mm, 40-pin QFN package (RoHS-6 compliant, exposed thermal pad). Pin functions are defined per the Si5332 Family Reference Manual Section 6.2 (Pin Descriptions – 40-Pin).

Pin/Terminal	Circuit Role	Design Meaning
XA / XB	Crystal input	Connects to fundamental-mode 16–50 MHz crystal; internal load capacitance programmable (2.5–21.5 pF)
CLKIN_2 / CLKIN_2#	Differential input	Accepts 10–250 MHz LVDS/LVPECL/HCSL; used for synchronous mode or backup reference
OUT0–OUT7	Differential clock outputs	Eight configurable outputs; OUT0–OUT3 have dedicated VDDO pins; OUT4–OUT7 grouped in Bank A/B sharing VDDO4/VDDO5
VDDO0–VDDO5	Output supply rails	Independent 1.8/2.5/3.3 V supplies per bank - enables mixed-voltage clock tree (e.g., 1.8 V FPGA + 3.3 V PHY)
SCL / SDA	I²C interface	Standard 100/400 kHz I²C bus for runtime configuration, profile switching, and NVM programming
OE#	Output enable	Active-low global output disable; may be assigned to universal HW pin via ClockBuilder Pro
IN0–IN6	Universal hardware inputs	Seven configurable pins - assignable to CLKIN_SEL, SS_EN#, OE#, FREQ_SEL, or I²C address select

Key Features

Feature	Design Value
MultiSynth fractional synthesis	Two independent paths support simultaneous non-integer output frequencies (e.g., 125 MHz + 156.25 MHz + 100.01 MHz)
Cross-point mux architecture	Any MultiSynth or integer divider output can drive any of 8 outputs - enables flexible clock tree mapping without redesign
Per-output signal format	LVDS/LVPECL/HCSL/LVCMOS selectable per pin - eliminates external translators in multi-standard systems (e.g., CPU + GPU + NIC)
Multi-profile NVM storage	Up to 16 configurations stored in on-chip NVM - allows field-upgradable clock plans for different operating modes or firmware versions
Spread spectrum control	Programmable down/center modulation (0.1–2.5% at 30–33 kHz) - reduces EMI peak emissions without affecting timing integrity
Glitchless frequency change	On-the-fly reconfiguration within same profile - maintains continuous clock output during dynamic rate adaptation (e.g., link training)

Applications

Server Clock Tree	Ethernet Switch Timing
Use Scenario: Generating synchronized clocks for CPU, memory controller, PCIe root complex, and onboard NIC in 1U/2U rack servers. IC Role / Device Role / Timing Role: Single-chip clock source replacing discrete oscillators and fanout buffers; delivers <200 fs jitter for Gen5/6 PCIe compliance. Use Value: Reduces BOM count by ≥7 components, eliminates inter-clock skew, and enables unified firmware-controlled frequency scaling across domains.	Use Scenario: Providing reference clocks to multiple 10/25/100 GbE PHYs, switch fabric ASICs, and packet buffer controllers in Layer 2/3 switches. IC Role / Device Role / Timing Role: High-isolation, multi-voltage clock generator with banked VDDO supporting 1.8 V SerDes and 3.3 V management interfaces. Use Value: Eliminates timing margin loss from board-level skew; per-output format config ensures direct compatibility with diverse PHY vendors' requirements.
Small Cell Baseband	Broadcast Video Processing
Use Scenario: Delivering phase-aligned sampling clocks to ADC/DACs, FPGA-based digital front-end (DFE), and fronthaul interface (eCPRI/JESD204B) in 4G/5G small cells. IC Role / Device Role / Timing Role: Low-jitter, multi-frequency synthesizer with deterministic latency - critical for TDD synchronization and MIMO beamforming. Use Value: Enables sub-100 ps inter-channel skew across 8 outputs, meeting 3GPP TR 38.803 fronthaul timing budgets without external delay tuning.	Use Scenario: Synchronizing SDI serializers, video processing FPGAs, HDMI transmitters, and audio sample-rate converters in broadcast cameras and production switchers. IC Role / Device Role / Timing Role: Precision clock generator supporting SMPTE ST 2059-2 PTP timing, 27/74.25/148.5 MHz video rates, and AES3 audio clocks. Use Value: Single-device support for all video/audio standards eliminates manual clock selection jumpers and reduces layout complexity in dense HD/4K PCBs.

Server Clock Tree

Ethernet Switch Timing

Use Scenario: Generating synchronized clocks for CPU, memory controller, PCIe root complex, and onboard NIC in 1U/2U rack servers.

IC Role / Device Role / Timing Role: Single-chip clock source replacing discrete oscillators and fanout buffers; delivers <200 fs jitter for Gen5/6 PCIe compliance.

Use Value: Reduces BOM count by ≥7 components, eliminates inter-clock skew, and enables unified firmware-controlled frequency scaling across domains.

Use Scenario: Providing reference clocks to multiple 10/25/100 GbE PHYs, switch fabric ASICs, and packet buffer controllers in Layer 2/3 switches.

IC Role / Device Role / Timing Role: High-isolation, multi-voltage clock generator with banked VDDO supporting 1.8 V SerDes and 3.3 V management interfaces.

Use Value: Eliminates timing margin loss from board-level skew; per-output format config ensures direct compatibility with diverse PHY vendors' requirements.

Small Cell Baseband

Broadcast Video Processing

Use Scenario: Delivering phase-aligned sampling clocks to ADC/DACs, FPGA-based digital front-end (DFE), and fronthaul interface (eCPRI/JESD204B) in 4G/5G small cells.

IC Role / Device Role / Timing Role: Low-jitter, multi-frequency synthesizer with deterministic latency - critical for TDD synchronization and MIMO beamforming.

Use Value: Enables sub-100 ps inter-channel skew across 8 outputs, meeting 3GPP TR 38.803 fronthaul timing budgets without external delay tuning.

Use Scenario: Synchronizing SDI serializers, video processing FPGAs, HDMI transmitters, and audio sample-rate converters in broadcast cameras and production switchers.

IC Role / Device Role / Timing Role: Precision clock generator supporting SMPTE ST 2059-2 PTP timing, 27/74.25/148.5 MHz video rates, and AES3 audio clocks.

Use Value: Single-device support for all video/audio standards eliminates manual clock selection jumpers and reduces layout complexity in dense HD/4K PCBs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332B-D-GM2R	Same 40-pin QFN package and architecture, but limited to integer-mode synthesis only (no fractional outputs)	Suitable for fixed-ratio clock trees (e.g., 125 MHz → 62.5 MHz → 31.25 MHz); cannot generate arbitrary frequencies like 100.01 MHz	Select when cost sensitivity outweighs flexibility needs and all required frequencies are integer multiples of reference
LMK5B33414RGZR	Texas Instruments device with 4 outputs, integrated 2.5 GHz VCO, and JESD204B SYSREF support; higher jitter (220 fs RMS)	Targeted at JESD204B-compliant data converters; lacks 8-output density and per-output format flexibility of SI5332D-D-GM2R	Prefer for RF/data converter timing where SYSREF alignment is mandatory; not a drop-in replacement for multi-protocol clock distribution

Compared with SI5332B-D-GM2R, the SI5332D-D-GM2R adds fractional synthesis for arbitrary frequency generation; compared with LMK5B33414RGZR, it provides double the output count, lower jitter, and broader signal format support - making it optimal for dense, multi-standard timing in networking and compute platforms.

Availability

SI5332D-D-GM2R is available at Aetrix Electronics and suitable for Ethernet switches, server motherboards, and 5G small cell baseband units requiring stable component supply, long-term lifecycle assurance, and factory-programmed configuration traceability.

Supply support for SI5332D-D-GM2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5332 family was designed to replace multiple discrete clock sources with a single, software-configurable IC - targeting high-density, low-jitter timing in cloud infrastructure, 5G infrastructure, and broadcast equipment.

FAQ

What is the maximum output frequency supported by the SI5332D-D-GM2R?

The SI5332D-D-GM2R supports a maximum output frequency of 200 MHz. This limit applies to all output formats (LVDS, LVPECL, HCSL, LVCMOS) and is specified for the Si5332D grade in the official Skyworks datasheet. Frequencies above 200 MHz require the Si5332A or Si5332C variants, which support up to 333.33 MHz.

Does the SI5332D-D-GM2R include an embedded crystal?

No, the SI5332D-D-GM2R does not include an embedded crystal. It belongs to the Si5332A/B/C/D series, which requires an external 16–50 MHz fundamental-mode crystal connected to XA/XB pins. Embedded crystal variants (e.g., Si5332E/F/G/H/L) use a factory-integrated 50 MHz MEMS resonator and carry different part number suffixes.

How many independent power supply domains does the SI5332D-D-GM2R support for its outputs?

The SI5332D-D-GM2R supports six independent output supply domains via VDDO0–VDDO5. Outputs OUT0–OUT3 each have dedicated VDDO pins, while OUT4–OUT7 are grouped into Bank A (VDDO4) and Bank B (VDDO5), enabling mixed-voltage operation such as 1.8 V SerDes and 3.3 V management interfaces from one device.

Can the SI5332D-D-GM2R generate PCIe Gen5 reference clocks?

Yes, the SI5332D-D-GM2R is PCIe Gen1 through Gen6 compliant. Its 190 fs RMS phase jitter (12 kHz–20 MHz) meets the PCIe Gen5 specification requirement of ≤250 fs RMS, and its 200 MHz maximum output covers the 100 MHz Gen5 reference clock with margin for spread spectrum and tolerance.

Is factory programming included with SI5332D-D-GM2R orders?

Yes, custom factory programming is included at no charge for SI5332D-D-GM2R when ordered with a ClockBuilder Pro–generated configuration file and corresponding NVM code. The device ships preprogrammed with the exact clock plan, eliminating the need for in-system programming during manufacturing.

SI5332D-D-GM2R Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 40-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Generator

PLL:: Yes

Input:: LVCMOS, Crystal

Output:: HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 3:8

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 200MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 40-QFN (6x6)

SI5332D-D-GM2R FAQ

1.How can I place an order for SI5332D-D-GM2R through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5332D-D-GM2R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5332D-D-GM2R reliable?

The price and inventory of SI5332D-D-GM2R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332D-D-GM2R is usually 5 days.

3.What payment methods are accepted for SI5332D-D-GM2R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332D-D-GM2R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5332D-D-GM2R?

SI5332D-D-GM2R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5332D-D-GM2R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5332D-D-GM2R?

For technical support, including SI5332D-D-GM2R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332D-D-GM2R requirements.

6.How does Aetrix verify that SI5332D-D-GM2R is sourced from the original manufacturer or authorized distributors?

All SI5332D-D-GM2R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332D-D-GM2R meets industry standards.

7.What is the process for return or replacement of SI5332D-D-GM2R?

All SI5332D-D-GM2R units undergo pre-shipment inspection (PSI). If there is an issue with SI5332D-D-GM2R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5332D-D-GM2R part is unused and in its original packaging.

Return procedure for SI5332D-D-GM2R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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