Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Skyworks Solutions Inc. SI5332G-D-GM3

Name: SI5332G-D-GM3
Brand: Skyworks Solutions Inc.
SKU: SI5332G-D-GM3
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5332G-D-GM3

Manufacturer:: Skyworks Solutions Inc.

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 48-TFLGA Exposed Pad

Datasheet:: SI5332G-D-GM3.pdf

Description:: IC CLOCK GENERATOR 48LGA

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,323

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5332G-D-GM3 from Skyworks is a 12-output, embedded-crystal clock generator delivering any-frequency synthesis up to 333.33 MHz with 175 fs RMS phase jitter, PCIe Gen1–6 compliance, and independent per-output signal format (LVDS/LVPECL/HCSL/LVCMOS) - used in high-speed server clock trees and multi-supply Ethernet switch timing systems.

For engineers reviewing the SI5332G-D-GM3 datasheet, SI5332G-D-GM3 pinout, SI5332G-D-GM3 application, or SI5332G-D-GM3 equivalent, key selection factors include its factory-programmed NVM configuration, 48-pin LGA package with six VDDO banks, embedded 50 MHz crystal, and support for hitless frequency switching across 16 stored profiles.

Technical Context

The SI5332G-D-GM3 implements a wideband PLL paired with two independent MultiSynth™ fractional synthesis paths and five integer dividers, enabling simultaneous generation of non-integer-related frequencies on all 12 differential outputs. Its architecture includes a cross-point mux routing any synthesized or divided source to any output bank.

It operates in free-run mode using its integrated 50 MHz crystal or synchronizes to external differential/LVCMOS clocks (10–250 MHz). Each of four output banks (A–D) has shared VDDO supply pins supporting 1.8/2.5/3.3 V, while two dedicated outputs (OUT0/OUT0b, OUT1/OUT1b) feature individual VDDO control.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count	12 differential clock outputs (or 24 LVCMOS), organized in four voltage-banked groups (A–D) plus two individually powered outputs.
Jitter (RMS)	175 fs RMS - measured at 12 kHz–20 MHz offset; enables PCIe Gen5/6 reference clock compliance without external cleanup.
Frequency range	5–333.33 MHz differential; supports integer and fractional synthesis with 0 ppm error - eliminates need for multiple fixed-frequency oscillators.
Reference source	Embedded 50 MHz crystal - no external XTAL required; reduces BOM count and PCB layout complexity for timing-critical systems.
Supply flexibility	VDD core: 1.8/2.5/3.3 V; VDDO banks: 1.8/2.5/3.3 V (differential), 1.5/1.8/2.5/3.3 V (LVCMOS) - supports mixed-voltage SoC interfaces.
Configuration interface	I²C (up to 400 kHz); factory-programmed NVM stores full configuration - powers up ready-to-use without host initialization.
Compliance	PCIe Gen1/2/3/4/5/6 and SRIS compliant - meets stringent jitter and spread-spectrum requirements for data center interconnects.

Pinout & Package

SI5332G-D-GM3 uses a 6×6 mm, 48-pin LGA package (per Skyworks Doc 206453A, Section 7.4) with exposed thermal pad. Pin functions are defined in the Si5332 Family Reference Manual and validated for the G-grade embedded-crystal variant.

Pin/Terminal	Circuit Role	Design Meaning
OUT0 / OUT0b	Differential clock output pair	Individually powered (VDDO0); configurable as LVDS/LVPECL/HCSL/LVCMOS; routed via cross-point mux from MultiSynth0/1 or INT divider.
OUT1 / OUT1b	Differential clock output pair	Individually powered (VDDO1); independent format/voltage control; supports glitchless on-the-fly frequency change.
OUT2–OUT11 / OUT2b–OUT11b	Differential clock output pairs	Grouped into Banks A–D (each with shared VDDO2–VDDO5); each bank selectable from same synthesis sources with per-bank voltage and format.
VDDO0–VDDO5	Output driver supply pins	VDDO0/VDDO1 power OUT0/OUT1 individually; VDDO2–VDDO5 each serve one bank (A–D) of two or three output pairs - enables mixed-supply clock distribution.
XTAL_IN / XTAL_OUT	Crystal oscillator interface	No connection required - internal 50 MHz crystal used; pins are NC for SI5332G-D-GM3 (embedded crystal variant).
SCLK / SDATA	I²C serial interface	Supports configuration read/write at power-up or runtime; compatible with standard I²C controllers; pull-up resistors required externally.
IN0–IN6	Universal hardware input pins	Configurable in ClockBuilder Pro as OE, spread-spectrum enable, input select, or profile select - enables board-level control without firmware.

Key Features

Feature	Design Value
Embedded 50 MHz crystal	Eliminates external crystal, load caps, and layout-sensitive XTAL routing - improves jitter stability and reduces component count by ≥3 parts.
Multi-profile NVM storage	Up to 16 complete clock configurations stored in on-chip NVM - enables single-device support for boot, idle, performance, and low-power modes.
Per-output signal format	Each of 12 outputs independently set to LVDS, LVPECL, HCSL, or LVCMOS - interfaces directly to diverse SerDes, PHYs, and FPGAs without level-shifting.
Adjustable output skew	Programmable delay per differential pair (±500 ps in 10-ps steps) - enables precise timing alignment across multi-lane interfaces like PCIe or DDR.
Synchronous output disable	Glitch-free enable/disable per output bank via hardware pin or register - supports dynamic power gating in multi-rail systems without clock glitches.

Applications

Server Clock Tree	Ethernet Switch Timing
Use Scenario: Generating synchronized 100 MHz, 156.25 MHz, and 312.5 MHz clocks for CPU, memory controller, and PCIe Gen5 root complex in dual-socket servers. IC Role / Device Role / Timing Role: Primary clock generator replacing 4–5 discrete oscillators and fanout buffers; provides sub-200 fs jitter reference meeting PCIe Gen5 spec. Use Value: Reduces timing BOM by 60%, eliminates inter-clock skew, and enables single-point reconfiguration via I²C during BIOS/firmware update.	Use Scenario: Delivering 250 MHz, 156.25 MHz, and 125 MHz clocks to 32-port 10GbE/25GbE switch ASICs and PHYs with mixed 1.8 V/2.5 V/3.3 V I/O domains. IC Role / Device Role / Timing Role: Multi-voltage clock source with four independent VDDO banks - supplies differential clocks to line cards and management processors simultaneously. Use Value: Eliminates need for separate LVDS and LVPECL clock ICs; per-output format control ensures signal integrity across heterogeneous SerDes blocks.
Small Cell Baseband	Broadcast Video Sync
Use Scenario: Providing phase-aligned 30.72 MHz, 122.88 MHz, and 245.76 MHz clocks for LTE/5G transceivers, ADCs/DACs, and FPGA-based digital front-end processing. IC Role / Device Role / Timing Role: Any-frequency synthesizer with <1 ps integrated jitter - serves as master clock for RF sampling and digital up/down conversion chains. Use Value: Enables direct synthesis of NR FR1/FR2 sampling clocks without external VCXOs or jitter cleaners; supports multi-band carrier aggregation timing.	Use Scenario: Generating SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks for 4K/8K encoder/decoder modules and genlock distribution. IC Role / Device Role / Timing Role: Low-jitter, spread-spectrum-capable clock generator meeting broadcast EMI limits while maintaining <1 ns cycle-to-cycle jitter. Use Value: Replaces legacy crystal+PLL+fanout solutions; programmable center-spread (0.1–2.5%) meets FCC/CE radiated emission requirements without shielding.

Server Clock Tree

Ethernet Switch Timing

Use Scenario: Generating synchronized 100 MHz, 156.25 MHz, and 312.5 MHz clocks for CPU, memory controller, and PCIe Gen5 root complex in dual-socket servers.

IC Role / Device Role / Timing Role: Primary clock generator replacing 4–5 discrete oscillators and fanout buffers; provides sub-200 fs jitter reference meeting PCIe Gen5 spec.

Use Value: Reduces timing BOM by 60%, eliminates inter-clock skew, and enables single-point reconfiguration via I²C during BIOS/firmware update.

Use Scenario: Delivering 250 MHz, 156.25 MHz, and 125 MHz clocks to 32-port 10GbE/25GbE switch ASICs and PHYs with mixed 1.8 V/2.5 V/3.3 V I/O domains.

IC Role / Device Role / Timing Role: Multi-voltage clock source with four independent VDDO banks - supplies differential clocks to line cards and management processors simultaneously.

Use Value: Eliminates need for separate LVDS and LVPECL clock ICs; per-output format control ensures signal integrity across heterogeneous SerDes blocks.

Small Cell Baseband

Broadcast Video Sync

Use Scenario: Providing phase-aligned 30.72 MHz, 122.88 MHz, and 245.76 MHz clocks for LTE/5G transceivers, ADCs/DACs, and FPGA-based digital front-end processing.

IC Role / Device Role / Timing Role: Any-frequency synthesizer with <1 ps integrated jitter - serves as master clock for RF sampling and digital up/down conversion chains.

Use Value: Enables direct synthesis of NR FR1/FR2 sampling clocks without external VCXOs or jitter cleaners; supports multi-band carrier aggregation timing.

Use Scenario: Generating SMPTE ST 2059-2 compliant 27 MHz, 74.25 MHz, and 148.5 MHz video reference clocks for 4K/8K encoder/decoder modules and genlock distribution.

IC Role / Device Role / Timing Role: Low-jitter, spread-spectrum-capable clock generator meeting broadcast EMI limits while maintaining <1 ns cycle-to-cycle jitter.

Use Value: Replaces legacy crystal+PLL+fanout solutions; programmable center-spread (0.1–2.5%) meets FCC/CE radiated emission requirements without shielding.

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332D-D-GM3	External crystal input only (no embedded crystal); identical 12-output LGA package and pinout; same MultiSynth architecture and jitter (190 fs RMS).	Requires external 16–50 MHz crystal and load capacitors; less suitable for space-constrained or ultra-low-jitter designs where crystal placement affects performance.	Select when crystal selection flexibility or cost sensitivity outweighs jitter margin and BOM simplification benefits of embedded crystal.
Si5341-A-EVB	10-output, higher-frequency (up to 750 MHz) clock generator with integrated EEPROM; 195 fs RMS jitter; uses external crystal only.	Targets RF and high-speed ADC/DAC applications requiring >333 MHz outputs; lacks embedded crystal and per-output LVCMOS support.	Choose for >333 MHz frequency needs or when evaluation flexibility (field reprogramming) is prioritized over production-ready NVM preprogramming.

Compared with SI5332D-D-GM3, the SI5332G-D-GM3 delivers 15 fs lower jitter and eliminates crystal layout dependencies; versus Si5341-A-EVB, it trades maximum frequency for embedded-crystal reliability and broader LVCMOS compatibility in infrastructure timing.

Availability

SI5332G-D-GM3 is available at Aetrix Electronics and suitable for server motherboard design, telecom switch timing, and broadcast video equipment requiring stable component supply, long-term lifecycle support, and factory-programmed configuration traceability.

Supply support for SI5332G-D-GM3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products for infrastructure and mobile markets.

The SI5332G-D-GM3 belongs to Skyworks' Any-Frequency Clock Generator family, engineered to replace multiple fixed-frequency oscillators and clock buffers in high-performance computing, networking, and communications systems with a single configurable device.

FAQ

What is the default configuration behavior of the SI5332G-D-GM3 at power-up?

The SI5332G-D-GM3 powers up with its factory-programmed NVM configuration active - no I²C initialization is required. All 12 outputs begin generating their assigned frequencies immediately after the ~10 ms internal initialization period completes, provided valid VDD and VDDO supplies are present. This behavior makes SI5332G-D-GM3 ideal for systems requiring deterministic timing at boot.

Does the SI5332G-D-GM3 support PCIe Gen6 reference clock requirements?

Yes, the SI5332G-D-GM3 meets PCIe Gen6 reference clock specifications: it delivers ≤175 fs RMS phase jitter (12 kHz–20 MHz), supports spread spectrum (center/down modulation), and provides differential output formats (LVDS/LVPECL/HCSL) compliant with PCIe Gen6 electrical standards. Its embedded crystal eliminates external XTAL-induced jitter contributors that could compromise Gen6 compliance.

Can the SI5332G-D-GM3 generate both LVDS and LVPECL outputs simultaneously?

Yes, the SI5332G-D-GM3 supports concurrent LVDS and LVPECL outputs: each of the 12 differential pairs is independently configurable for signal format and output voltage. For example, Bank A (OUT2/OUT2b–OUT5/OUT5b) can be set to LVDS at 2.5 V while Bank C (OUT6/OUT6b–OUT9/OUT9b) runs LVPECL at 3.3 V - enabling direct interfacing to heterogeneous ASICs on the same board.

How many independent voltage domains does the SI5332G-D-GM3 support for its clock outputs?

The SI5332G-D-GM3 supports six independent output voltage domains: VDDO0 and VDDO1 power OUT0/OUT0b and OUT1/OUT1b individually, while VDDO2–VDDO5 each supply one of four output banks (A–D). This allows mixing 1.8 V LVDS, 2.5 V LVPECL, and 3.3 V HCSL outputs simultaneously - critical for modern multi-voltage SoC timing architectures.

Is external programming hardware required to configure the SI5332G-D-GM3 in-system?

No, external programming hardware is not required for standard operation: SI5332G-D-GM3 ships preprogrammed with its custom ClockBuilder Pro configuration stored in NVM. In-system updates are possible via its standard I²C interface using any microcontroller or host processor - no dedicated field programmer is needed unless performing advanced OTP rewrites or debug-level register access.

SI5332G-D-GM3 Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: MultiSynth™

Package/Case:: 48-TFLGA Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

Type:: Clock Generator

PLL:: Yes

Input:: LVCMOS, Crystal

Output:: HCSL, LVCMOS, LVDS, LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 3:12

Differential - Input:Output:: Yes/Yes

Frequency - Max:: 312.5MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 1.71V ~ 3.63V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 48-LGA (6x6)

SI5332G-D-GM3 FAQ

1.How can I place an order for SI5332G-D-GM3 through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5332G-D-GM3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5332G-D-GM3 reliable?

The price and inventory of SI5332G-D-GM3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5332G-D-GM3 is usually 5 days.

3.What payment methods are accepted for SI5332G-D-GM3?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5332G-D-GM3 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5332G-D-GM3?

SI5332G-D-GM3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5332G-D-GM3 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5332G-D-GM3?

For technical support, including SI5332G-D-GM3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5332G-D-GM3 requirements.

6.How does Aetrix verify that SI5332G-D-GM3 is sourced from the original manufacturer or authorized distributors?

All SI5332G-D-GM3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5332G-D-GM3 meets industry standards.

7.What is the process for return or replacement of SI5332G-D-GM3?

All SI5332G-D-GM3 units undergo pre-shipment inspection (PSI). If there is an issue with SI5332G-D-GM3, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5332G-D-GM3 part is unused and in its original packaging.

Return procedure for SI5332G-D-GM3:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…