Skyworks Solutions Inc. SI5334B-B04153-GM
- Part No.:
- SI5334B-B04153-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5334B-B04153-GM.pdf
- Description:
- 4-OUTPUT, ANY FREQUENCY(<350MHZ)
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5334B-B04153-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, 0 ppm frequency accuracy, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats up to 710 MHz - deployed in Ethernet switch/router and PCI Express 3.0 timing systems.
For engineers reviewing the SI5334B-B04153-GM datasheet, SI5334B-B04153-GM pinout, SI5334B-B04153-GM application, or SI5334B-B04153-GM equivalent, this page delivers verified specifications, factory-programmed configuration details, MultiSynth synthesis architecture, loss-of-lock alarm behavior, and pin-controlled frequency/phase adjustment capability - all confirmed for the B04153 variant.
Technical Context
The SI5334B-B04153-GM implements a fractional-N PLL with integrated VCO and four independent MultiSynth dividers, enabling zero-ppm error synthesis on each of four differential outputs. Input flexibility includes 8–30 MHz crystal or 5–710 MHz differential/single-ended reference clocks.
Each output driver supports independent voltage selection (1.5/1.8/2.5/3.3 V), format selection (LVPECL to CMOS), and programmable phase offset (±45 ns in 20 ps steps). The device operates from 1.8/2.5/3.3 V core supply and features pin-controlled glitchless frequency increment/decrement (1 ppm steps) on CLK0A/B only.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B), each independently configurable |
| Frequency range | 0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS with integer-related constraints |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), validated for GbE and OC-12 compliance |
| Frequency accuracy | True 0 ppm error across all outputs via MultiSynth fractional synthesis |
| Supply voltages | Core: 1.8/2.5/3.3 V; Output buffers: 1.4–3.63 V per channel, independently selectable |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad |
| Operating temperature | –40 °C to +85 °C ambient, qualified for industrial embedded and telecom line card use |
Pinout & Package
SI5334B-B04153-GM is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5334 family layout and match the transparent top view shown in the datasheet Rev. 1.3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1 / IN2 | Differential reference input (primary) | Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enabled |
| IN3 / IN4 | Single-ended reference input | Supports 5–200 MHz CMOS-level input; VIH = 0.7×VDD, VIL = 0.3×VDD |
| IN5 / IN6 | Differential feedback input (FDBK/FDBKB) | Enables zero-delay mode when connected to selected output (e.g., CLK0A/B) |
| CLK0A / CLK0B | Differential output 0 | Primary output with pin-controlled frequency increment/decrement (1 ppm steps) |
| CLK1A / CLK1B | Differential output 1 | Fully configurable format/voltage/frequency; no pin-control frequency adjust |
| CLK2A / CLK2B | Differential output 2 | Independent MultiSynth divider; supports HCSL up to 250 MHz or LVDS up to 350 MHz |
| CLK3A / CLK3B | Differential output 3 | Final output channel; phase-adjustable ±45 ns in 20 ps steps |
| VDDO0–VDDO3 | Output buffer supplies | Four independent power pins (1.4–3.63 V) - one per output pair - enable mixed-voltage system interfacing |
| VDD | Core supply | 1.8/2.5/3.3 V ± tolerance; powers PLL, MultiSynth, control logic, and NVM |
| LOSLOL | Loss-of-signal/loss-of-lock open-drain flag | Asserts low within 5 µs of input failure or PLL unlock; deasserts within 1 µs of recovery |
| OEB | Output enable (active-low) | Global disable for all four differential outputs; high-Z state preserves signal integrity during standby |
| RSVD_GND | Reserved ground | Internal test pin; must be connected to GND per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth frequency synthesis | Four independent fractional-N synthesizers deliver true 0 ppm accuracy on each output without external loop filters |
| Pin-controlled frequency adjust | Glitchless ±1 ppm step increments on CLK0A/B only, updated at ≤1.5 MHz rate - enables margin testing and dynamic clock tuning |
| Programmable phase offset | ±45 ns range in 20 ps resolution per output - critical for skew-sensitive SerDes alignment (e.g., PCIe Gen3) |
| Flexible output drivers | Per-output selection of LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL with independent VDDO (1.5–3.3 V) |
| Zero-delay mode | External feedback via IN5/IN6 enables phase-nullified clock distribution - eliminates propagation delay between reference and output |
| Loss-of-signal detection | Dedicated LOSLOL pin asserts within 5 µs of input failure or PLL unlock - supports fail-safe system monitoring |
Applications
| Ethernet Switch/Router Timing | PCI Express 3.0 Clocking |
|---|---|
Use Scenario: Synchronizing multi-lane 10 GbE PHYs and packet processors in Layer 3 switches with sub-100 ps skew tolerance. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (PCIe), 250 MHz (PHY interface), and 100 MHz (management controller) clocks. Use Value: Eliminates need for multiple discrete oscillators; 0.7 ps RMS jitter ensures <1.5 UI total jitter margin at 10.3125 Gbps. |
Use Scenario: Generating compliant reference clocks for CPU, GPU, and NVMe controllers in server motherboards. IC Role / Device Role / Timing Role: Supplies 100 MHz HCSL PCIe Gen3 reference to root complex and endpoints while supporting spread spectrum modulation. Use Value: Meets PCIe 3.0 RMS jitter spec (<0.45 ps) and SSC compliance - reduces EMI without sacrificing timing margin. |
| Broadcast Video/Audio Sync | Processor & FPGA Clocking |
Use Scenario: Aligning SMPTE 2110 video streams, AES67 audio, and genlock signals across IP-based broadcast infrastructure. IC Role / Device Role / Timing Role: Generates synchronized 74.25 MHz (HD-SDI), 148.5 MHz (3G-SDI), 297 MHz (12G-SDI), and 27 MHz (audio sample clock) outputs. Use Value: Phase-adjustable outputs enable precise inter-frame alignment; 0 ppm accuracy prevents long-term drift in multi-device workflows. |
Use Scenario: Providing differentiated clocks to heterogeneous SoCs (ARM cores, DSPs, DDR interfaces) and Xilinx/Intel FPGAs in industrial vision systems. IC Role / Device Role / Timing Role: Delivers 500 MHz LVDS to FPGA transceivers, 200 MHz CMOS to ARM APU, 133 MHz SSTL to DDR3 memory, and 100 MHz HSTL to real-time co-processors. Use Value: Independent VDDO per output allows direct interface to mixed-voltage subsystems - avoids level shifters and board space overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05189-GM | Higher integration: 8 outputs, I²C programmability, lower jitter (0.35 ps RMS), but larger 32-QFN package | Required for designs needing >4 outputs or field reconfiguration; not pin-compatible | Select when future scalability or runtime tuning is needed - SI5334B-B04153-GM remains optimal for fixed, cost-sensitive 4-output deployments. |
| ICS853S01AGI-01LFT | Fixed-frequency (100/125/156.25 MHz), no frequency synthesis; 1.2 ps RMS jitter; 24-TSSOP package | Suitable only for static clock trees - lacks any-frequency generation, phase adjust, or spread spectrum | Choose only if design uses only standard frequencies and requires lowest BOM cost - SI5334B-B04153-GM adds essential flexibility for evolving interface standards. |
Compared with Si5332A-D05189-GM and ICS853S01AGI-01LFT, SI5334B-B04153-GM uniquely balances pin-controlled simplicity, 0 ppm synthesis accuracy, and 4-output density in a 4×4 mm QFN - making it ideal for space-constrained, factory-programmed timing applications where field reprogramming is unnecessary.
Availability
SI5334B-B04153-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCI Express 3.0 clocking, and broadcast video/audio synchronization requiring stable component supply and guaranteed long-term manufacturability.
Supply support for SI5334B-B04153-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for communications, automotive, and industrial markets.
The Si5334 product line was engineered for high-density, low-jitter clock generation in networking and datacenter equipment - delivering factory-programmed, pin-configurable timing with MultiSynth synthesis to replace multiple discrete oscillators.
FAQ
What is the factory-programmed configuration of SI5334B-B04153-GM?
The SI5334B-B04153-GM is pre-programmed by Skyworks with a specific frequency plan, output formats, voltage levels, and phase offsets stored in one-time-programmable (OTP) memory. Upon power-up, it immediately generates its assigned outputs without external configuration - eliminating boot-time delays and I²C dependencies. This configuration is immutable after programming and matches the B04153 variant definition in Skyworks documentation.
Does SI5334B-B04153-GM support spread spectrum clocking (SSC)?
Yes, SI5334B-B04153-GM supports PCI Express 2.0-compliant spread spectrum on any output clock operating at exactly 100 MHz with its Rn divider set to 1. It delivers –0.5% frequency deviation at 30–33 kHz modulation rate. SSC is not available on other frequencies or output formats - this capability is confirmed in Table 3 and Section 2.10 of the Rev. 1.3 datasheet.
Can SI5334B-B04153-GM generate 710 MHz on all four outputs simultaneously?
No. While SI5334B-B04153-GM supports up to 710 MHz on LVPECL/LVDS outputs, only two unique frequencies above Fvco/8 can be generated simultaneously - specifically Fvco/4 and Fvco/6. Full 710 MHz operation requires integer-related frequencies and is limited to one or two outputs depending on VCO constraints. This restriction is explicitly stated in Note 4 of Table 4.
What is the function of the RSVD_GND pin on SI5334B-B04153-GM?
The RSVD_GND pin on SI5334B-B04153-GM is an internal test node designated "Reserved Ground" in the datasheet. It must be connected to system ground per Skyworks layout guidelines (Section 7) to ensure proper thermal dissipation and signal integrity. Leaving it unconnected or floating may compromise jitter performance and thermal stability - it is not an optional or unused pin.
How does the LOSLOL pin behave during power-up and reference loss?
The LOSLOL pin on SI5334B-B04153-GM is an open-drain alarm that asserts low within 2.6–5 µs of input clock loss or PLL unlock, and deasserts within 0.01–1 µs of signal restoration or lock reacquisition. During power-up, it remains high until the PLL achieves lock (typically within 25 ms acquisition time), then transitions to active-high idle state - providing deterministic fault signaling for system supervisors.
SI5334B-B04153-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5334B-B04153-GM FAQ
1.How can I place an order for SI5334B-B04153-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5334B-B04153-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5334B-B04153-GM reliable?
The price and inventory of SI5334B-B04153-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334B-B04153-GM is usually 5 days.
3.What payment methods are accepted for SI5334B-B04153-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334B-B04153-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5334B-B04153-GM?
SI5334B-B04153-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5334B-B04153-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5334B-B04153-GM?
For technical support, including SI5334B-B04153-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334B-B04153-GM requirements.
6.How does Aetrix verify that SI5334B-B04153-GM is sourced from the original manufacturer or authorized distributors?
All SI5334B-B04153-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334B-B04153-GM meets industry standards.
7.What is the process for return or replacement of SI5334B-B04153-GM?
All SI5334B-B04153-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334B-B04153-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5334B-B04153-GM part is unused and in its original packaging.
Return procedure for SI5334B-B04153-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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