Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334B-B04153-GMR

Name: SI5334B-B04153-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5334B-B04153-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5334B-B04153-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334B-B04153-GMR.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<350MHZ)

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,745

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5334B-B04153-GMR from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, 0 ppm frequency accuracy, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats up to 710 MHz - deployed in Ethernet switch/router and PCIe 3.0 timing systems.

For engineers reviewing the SI5334B-B04153-GMR datasheet, SI5334B-B04153-GMR pinout, SI5334B-B04153-GMR application, or SI5334B-B04153-GMR equivalent, key selection considerations include its factory-programmed configuration, 4×4 mm 24-QFN package, independent output voltage per driver (1.5/1.8/2.5/3.3 V), core supply flexibility (1.8/2.5/3.3 V), and glitchless 1 ppm frequency increment/decrement capability on CLK0A/B.

Technical Context

The SI5334B-B04153-GMR integrates a fractional-N PLL with on-chip VCO and four independent MultiSynth synthesis stages, each supporting non-integer frequency division to generate any output frequency from 0.16 MHz to 710 MHz. Input reference options include 8–30 MHz crystal or 5–710 MHz differential/single-ended clock signals.

Its architecture enables zero-delay mode via external feedback to FDBK/FDBKB pins, loss-of-lock and loss-of-signal detection via LOSLOL pin, and pin-controlled phase adjustment (±45 ns range, <20 ps step) and frequency tuning (1 ppm steps, up to 350 MHz range) - all without I²C interface or host processor intervention.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B), each independently configurable
Frequency range	0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS with specific divider settings
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), enabling compliance with PCIe 3.0 and 10 GbE jitter budgets
Frequency accuracy	True 0 ppm error across all outputs due to MultiSynth fractional synthesis with no PFD spurs
Supply voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad - optimized for high-density PCB layout
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments

Pinout & Package

SI5334B-B04153-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad (pin 24 = GND). Pin assignments are fixed per Skyworks Rev. 1.3 datasheet Figure 2 (Transparent Top View).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input (primary)	Accepts 5–710 MHz AC-coupled differential clock; internal 10 kΩ termination; requires external 100 Ω load
IN3 / IN4	Single-ended reference input	Supports 5–200 MHz CMOS-level clock; VIH = 0.7×VDD, VIL = 0.3×VDD; 4 pF input capacitance
IN5 / IN6	Differential feedback input (FDBK/FDBKB)	Enables zero-delay mode when connected to CLK0A/B; supports same frequency range as IN1/IN2
CLK0A / CLK0B – CLK3A / CLK3B	Differential clock outputs (4 pairs)	Each pair supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL; individually voltage- and format-configurable
VDDO0–VDDO3	Independent output buffer supplies	Per-output 1.5/1.8/2.5/3.3 V supply pins - enable mixed-voltage system interfacing without level shifters
VDD	Core supply	1.8/2.5/3.3 V ±10%; 45 mA typical current at 100 MHz on all outputs with 25 MHz refclk
LOSLOL	Loss-of-signal/loss-of-lock open-drain alarm	Asserts low within 5 µs of signal loss or PLL unlock; sinks 3 mA; requires external pull-up
OEB	Output enable (active-low)	Global disable for all four differential output pairs; synchronous assertion/deassertion

Key Features

Feature	Design Value
MultiSynth frequency synthesis	Four independent fractional-N synthesis engines deliver any output frequency from 0.16 MHz to 710 MHz with zero ppm error
Pin-controlled frequency tuning	Glitchless 1 ppm step size on CLK0A/B enables real-time margining and dynamic frequency adaptation without firmware
Programmable phase offset	±45 ns adjustment range per output with <20 ps resolution supports precise inter-clock alignment in multi-FPGA systems
Spread spectrum (SSC)	PCIe 2.0-compliant SSC available on any 100 MHz output with Rn divider = 1 - reduces EMI by up to 10 dB
Zero-delay feedback mode	External feedback to IN5/IN6 eliminates static phase offset between reference and selected output - critical for deterministic latency paths

Applications

Ethernet Switch/Router Timing	PCI Express 3.0 Clocking
Use Scenario: Synchronizing multiple 10 GbE PHYs, packet processors, and switch fabric ASICs in Layer 3 routing platforms. IC Role / Device Role / Timing Role: Primary quad-output clock source delivering 156.25 MHz, 125 MHz, 100 MHz, and 25 MHz with sub-1 ps jitter to meet IEEE 802.3ae and PCIe Gen3 requirements. Use Value: Eliminates need for multiple discrete oscillators or clock buffers; single-device solution reduces BOM count and board area by >40%.	Use Scenario: Providing reference clocks to CPU, GPU, and peripheral controllers in server motherboards with PCIe 3.0 x16 slots. IC Role / Device Role / Timing Role: Generating 100 MHz HCSL clocks with <0.45 ps RMS jitter (PCIe 3.0 spec limit: 1.0 ps RMS) across four independent lanes. Use Value: Meets Intel Clock Jitter Tool v1.6.4 validation for PCIe 3.0 common clock architecture without additional jitter cleaning.
Broadcast Video/Audio Sync	FPGA & Processor Clocking
Use Scenario: Aligning SMPTE 2082 (12G-SDI), AES67 audio, and genlock signals in IP-based broadcast infrastructure. IC Role / Device Role / Timing Role: Delivering 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz simultaneously with <10 ps pk-pk period jitter for frame-accurate media transport. Use Value: Enables single-chip synchronization of video encoder, audio DSP, and network interface - avoids timing skew-induced lip-sync errors.	Use Scenario: Supplying configurable clocks to Xilinx Versal, Intel Agilex, and ARM-based SoCs requiring mixed-voltage I/O banks. IC Role / Device Role / Timing Role: Providing 50 MHz CMOS, 100 MHz LVDS, 200 MHz HSTL, and 350 MHz SSTL from one device with independent VDDO per bank. Use Value: Removes need for voltage translators or separate clock ICs per I/O standard - simplifies power domain partitioning.

Ethernet Switch/Router Timing

PCI Express 3.0 Clocking

Use Scenario: Synchronizing multiple 10 GbE PHYs, packet processors, and switch fabric ASICs in Layer 3 routing platforms.

IC Role / Device Role / Timing Role: Primary quad-output clock source delivering 156.25 MHz, 125 MHz, 100 MHz, and 25 MHz with sub-1 ps jitter to meet IEEE 802.3ae and PCIe Gen3 requirements.

Use Value: Eliminates need for multiple discrete oscillators or clock buffers; single-device solution reduces BOM count and board area by >40%.

Use Scenario: Providing reference clocks to CPU, GPU, and peripheral controllers in server motherboards with PCIe 3.0 x16 slots.

IC Role / Device Role / Timing Role: Generating 100 MHz HCSL clocks with <0.45 ps RMS jitter (PCIe 3.0 spec limit: 1.0 ps RMS) across four independent lanes.

Use Value: Meets Intel Clock Jitter Tool v1.6.4 validation for PCIe 3.0 common clock architecture without additional jitter cleaning.

Broadcast Video/Audio Sync

FPGA & Processor Clocking

Use Scenario: Aligning SMPTE 2082 (12G-SDI), AES67 audio, and genlock signals in IP-based broadcast infrastructure.

IC Role / Device Role / Timing Role: Delivering 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz simultaneously with <10 ps pk-pk period jitter for frame-accurate media transport.

Use Value: Enables single-chip synchronization of video encoder, audio DSP, and network interface - avoids timing skew-induced lip-sync errors.

Use Scenario: Supplying configurable clocks to Xilinx Versal, Intel Agilex, and ARM-based SoCs requiring mixed-voltage I/O banks.

IC Role / Device Role / Timing Role: Providing 50 MHz CMOS, 100 MHz LVDS, 200 MHz HSTL, and 350 MHz SSTL from one device with independent VDDO per bank.

Use Value: Removes need for voltage translators or separate clock ICs per I/O standard - simplifies power domain partitioning.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08189-GM	Higher integration: 8 outputs, integrated EEPROM, I²C programmability; larger 32-QFN (5×5 mm)	Requires firmware initialization; better suited for dynamically reconfigured systems vs. fixed pin-control use cases	Select when field reprogramming or >4 outputs are needed; not pin-compatible with SI5334B-B04153-GMR
ICS8430I-01T	Lower jitter (0.45 ps RMS), but only 2 outputs; no frequency/phase tuning; fixed 3.3 V core and I/O	Limited to dual-clock applications; lacks spread spectrum and zero-delay mode	Choose for ultra-low-jitter dual-output needs where configurability is secondary to jitter performance

Compared with SI5334B-B04153-GMR, Si5332A-D08189-GM adds programmability at the cost of pin control simplicity and footprint, while ICS8430I-01T trades output count and feature depth for marginal jitter improvement - making SI5334B-B04153-GMR optimal for fixed-function, space-constrained quad-clock systems.

Availability

SI5334B-B04153-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe 3.0 clocking, and broadcast video/audio synchronization requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for SI5334B-B04153-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si5334 family is designed for high-performance, low-jitter clock generation in datacenter, telecom, and broadcast infrastructure - emphasizing pin-controlled simplicity, multi-format flexibility, and factory-programmed reliability over software-driven complexity.

FAQ

What is the factory-programmed configuration of SI5334B-B04153-GMR?

The SI5334B-B04153-GMR is factory-programmed with a fixed configuration stored in one-time-programmable (OTP) memory. Upon power-up, it operates immediately without external configuration - delivering pre-defined frequencies, output formats, voltage levels, and phase offsets. This eliminates boot-time dependencies and ensures deterministic timing behavior critical for carrier-grade systems.

Does SI5334B-B04153-GMR support spread spectrum clocking (SSC)?

Yes, SI5334B-B04153-GMR supports PCIe 2.0-compliant spread spectrum on any output clock operating at exactly 100 MHz with its Rn divider set to 1. The modulation rate is 30–33 kHz with ±0.5% frequency deviation - reducing electromagnetic interference without violating PCIe timing margins.

Can SI5334B-B04153-GMR generate 710 MHz outputs?

Yes, SI5334B-B04153-GMR can generate 710 MHz outputs using LVPECL or LVDS format, but only under specific conditions: the MultiSynth output must be configured above Fvco/8, and only two unique frequencies above Fvco/8 (e.g., Fvco/4 and Fvco/6) may be active simultaneously per Skyworks Rev. 1.3 datasheet Section 4.

What is the function of the LOSLOL pin on SI5334B-B04153-GMR?

The LOSLOL pin on SI5334B-B04153-GMR is an open-drain alarm output that asserts low within 5 µs of either loss-of-signal (on IN1/IN2 or IN3/IN4) or loss-of-lock (PLL unlock). It sinks up to 3 mA and requires an external pull-up resistor - enabling system-level fault monitoring without additional logic.

Is SI5334B-B04153-GMR compatible with 1.8 V core supply operation?

Yes, SI5334B-B04153-GMR fully supports 1.8 V core supply operation (VDD = 1.71–1.98 V), drawing 45 mA typical current at 100 MHz on all outputs with 25 MHz reference clock. Its output buffers also support 1.5 V and 1.8 V VDDO rails - enabling direct interfacing with low-voltage FPGAs and ASICs.

SI5334B-B04153-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334B-B04153-GMR FAQ

1.How can I place an order for SI5334B-B04153-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334B-B04153-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334B-B04153-GMR reliable?

The price and inventory of SI5334B-B04153-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334B-B04153-GMR is usually 5 days.

3.What payment methods are accepted for SI5334B-B04153-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334B-B04153-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334B-B04153-GMR?

SI5334B-B04153-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334B-B04153-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334B-B04153-GMR?

For technical support, including SI5334B-B04153-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334B-B04153-GMR requirements.

6.How does Aetrix verify that SI5334B-B04153-GMR is sourced from the original manufacturer or authorized distributors?

All SI5334B-B04153-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334B-B04153-GMR meets industry standards.

7.What is the process for return or replacement of SI5334B-B04153-GMR?

All SI5334B-B04153-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5334B-B04153-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334B-B04153-GMR part is unused and in its original packaging.

Return procedure for SI5334B-B04153-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…