Skyworks Solutions Inc. SI5334C-B04088-GM
- Part No.:
- SI5334C-B04088-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5334C-B04088-GM.pdf
- Description:
- 4-OUTPUT, ANY FREQUENCY(<200MHZ)
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5334C-B04088-GM from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz using MultiSynth fractional-N synthesis, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, and operates from 1.8/2.5/3.3 V core and output supplies - deployed in PCIe 3.0 timing, FPGA clocking, and broadcast video systems.
For engineers reviewing the SI5334C-B04088-GM datasheet, SI5334C-B04088-GM pinout, SI5334C-B04088-GM application, or SI5334C-B04088-GM equivalent, key selection considerations include its 4× independent output frequency/phase/format configurability, factory-programmed zero-ppm accuracy, 24-QFN package compatibility, and support for glitchless 1 ppm frequency increment/decrement on CLK0A/B.
Technical Context
The SI5334C-B04088-GM integrates a fully on-chip fractional-N PLL (phase detector, charge pump, loop filter, VCO, R/N dividers) and four independent MultiSynth output synthesis stages, each capable of integer or fractional division to generate any output frequency up to 710 MHz. Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.
Each output driver supports independent voltage supply (1.5/1.8/2.5/3.3 V), selectable signal format, and features <20 ps phase step resolution over ±45 ns range. The device implements pin-controlled frequency increment/decrement (1 ppm steps, glitchless) on CLK0A/B only and supports PCI Express–compliant spread spectrum on 100 MHz outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B), each independently configurable |
| Frequency range | 0.16–710 MHz per output; supports 350 MHz integer mode and select higher frequencies (e.g., 710 MHz) via fractional synthesis |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); enables compliance with PCIe 3.0 (≤0.45 ps RMS) and GbE timing budgets |
| Frequency accuracy | True 0 ppm error across all outputs due to MultiSynth fractional synthesis with no PFD spurs or reference feedthrough |
| Supply voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad - optimized for high-density PCB layouts |
| Operating temperature | –40 °C to +85 °C ambient - qualified for industrial and telecom line card environments |
Pinout & Package
SI5334C-B04088-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin assignments follow the standard Si5334 pinout defined in Skyworks Rev. 1.3 datasheet (page 23), with dedicated input (IN1–IN7), output (CLK0A/B–CLK3A/B), supply (VDD, VDDO0–VDDO3), control (OEB, LOSLOL), and reserved (RSVD_GND) terminals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK0A / CLK0B | Differential output pair 0 | Primary output channel supporting frequency increment/decrement; configurable as LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL |
| CLK1A / CLK1B | Differential output pair 1 | Independent output with full format/voltage/frequency configuration; no frequency inc/dec capability |
| CLK2A / CLK2B | Differential output pair 2 | Independent output; supports phase adjustment (±45 ns, 20 ps steps) and spread spectrum (if 100 MHz) |
| CLK3A / CLK3B | Differential output pair 3 | Independent output; same capabilities as CLK2A/B; used for multi-clock domain synchronization |
| IN1 / IN2, IN5 / IN6 | Differential reference inputs | Accept 5–710 MHz AC-coupled differential clocks; require external 100 Ω termination |
| IN3 / IN4 | Single-ended reference inputs | Support CMOS/SSTL/HSTL inputs (5–350 MHz); DC-coupled with internal biasing |
| VDD | Core supply | 1.8/2.5/3.3 V supply for PLL, logic, and MultiSynth blocks; decoupling critical for jitter performance |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V per output pair - enables mixed-voltage system interfacing |
| OEB | Output enable bar | Active-low global output disable; synchronous assertion prevents glitches during power sequencing |
| LOSLOL | Loss-of-signal/loss-of-lock indicator | Open-drain output asserting low on input clock loss or PLL unlock; supports system fault monitoring |
| RSVD_GND | Reserved ground | Internally connected to die substrate; must be tied to PCB ground plane for EMI and thermal performance |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth fractional-N synthesis | Enables any-frequency generation (0.16–710 MHz) per output with zero ppm error and <0.7 ps RMS jitter - eliminates need for multiple crystals or discrete synthesizers |
| Independent output configuration | Each of four differential outputs supports separate voltage (1.5–3.3 V), format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), and frequency - simplifies multi-protocol board design |
| Glitchless frequency increment/decrement | 1 ppm step size on CLK0A/B only, updated at ≤1.5 MHz rate - enables real-time margin testing and dynamic frequency tuning without clock interruption |
| Programmable phase offset | ±45 ns range with <20 ps resolution per output - allows precise inter-clock alignment for SerDes deskew and TSN time synchronization |
| PCIe-compliant spread spectrum | Available on any 100 MHz output when Rn divider = 1; ±0.5% deviation at 30–33 kHz - reduces EMI peak emissions for FCC/CE certification |
Applications
| Ethernet Switch Timing | PCIe 3.0 Clock Distribution |
|---|---|
Use Scenario: Synchronizing 10 GbE PHYs, packet processors, and switch fabric ASICs requiring ultra-low-jitter, multi-frequency clocks. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 156.25 MHz (XAUI), 125 MHz (SGMII), 100 MHz (PCIe REFCLK), and 25 MHz (management) clocks. Use Value: Eliminates four discrete oscillators; 0.7 ps RMS jitter ensures <1 UI eye opening margin at 10.3125 Gbps; pin control enables field tuning without firmware. | Use Scenario: Delivering compliant reference clocks to CPU, GPU, and NVMe controllers in server motherboards and add-in cards. IC Role / Device Role / Timing Role: Generates 100 MHz PCIe 3.0 REFCLK with <0.45 ps RMS jitter and optional spread spectrum, plus auxiliary clocks for USB 3.0 and SATA. Use Value: Meets Intel Clock Jitter Tool v1.6.4 requirements; independent VDDO per output avoids level-shifter ICs; zero-ppm accuracy prevents link training failures. |
| Broadcast Video Timing | FPGA-Based Test Equipment |
Use Scenario: Generating SMPTE ST 2082 (12G-SDI), ST 2081 (6G-SDI), and ST 424 (3G-SDI) reference clocks in video routers and converters. IC Role / Device Role / Timing Role: Produces 297 MHz (12G), 148.5 MHz (6G), 74.25 MHz (3G), and 27 MHz (genlock) from single crystal input. Use Value: MultiSynth eliminates need for multiple TCXOs; phase adjustment aligns SDI pixel clocks across parallel lanes; jitter <1 ps RMS preserves eye diagram integrity. | Use Scenario: Providing programmable stimulus clocks (10–500 MHz) and sampling clocks (same range) for high-speed digital pattern generators and logic analyzers. IC Role / Device Role / Timing Role: Four outputs serve as independent clock sources for DUT interface, ADC sampling, FPGA logic, and trigger generation. Use Value: Frequency increment/decrement enables automated margin testing; 20 ps phase steps allow sub-cycle timing calibration; 24-QFN footprint saves space on dense test PCBs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D05888-GM | Higher integration: includes integrated crystal, lower jitter (0.35 ps RMS), I²C programmability, but larger 32-QFN package | Preferred for new designs requiring lowest jitter and crystal integration; not pin-compatible with SI5334C-B04088-GM | Select when jitter budget is <0.4 ps RMS and board space allows 5 mm × 5 mm footprint |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (no any-frequency synthesis); 1.2 ps RMS jitter; 3.3 V only; 32-TQFP package | Suitable only for static clock trees (e.g., fixed 100/125/156.25 MHz); lacks phase/frequency tuning or multi-voltage support | Choose only if design uses only pre-defined frequencies and requires legacy TQFP assembly |
Compared with Si5332A-D05888-GM and ICS8430I-01T, SI5334C-B04088-GM uniquely balances pin-controlled flexibility, 0.7 ps RMS jitter, 24-QFN compactness, and factory-programmed zero-ppm accuracy - making it optimal for cost-sensitive, space-constrained industrial and telecom timing where field reprogramming is unnecessary.
Availability
SI5334C-B04088-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe 3.0 clock distribution, and broadcast video/audio timing requiring stable component supply, long-term lifecycle assurance, and consistent factory-programmed configurations.
Supply support for SI5334C-B04088-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for communications, automotive, and industrial markets.
The Si5334 family is designed for high-performance, multi-protocol clock generation in space-constrained systems - delivering any-frequency synthesis, ultra-low jitter, and flexible output formatting without requiring microcontroller intervention.
FAQ
What is the maximum output frequency supported by SI5334C-B04088-GM?
The SI5334C-B04088-GM supports up to 710 MHz on differential outputs (LVPECL/LVDS) when operating in fractional synthesis mode above Fvco/8. For integer-mode operation - required for lowest jitter - the maximum is 350 MHz. The datasheet confirms 710 MHz is achievable on CLK0A/B, CLK1A/B, CLK2A/B, and CLK3A/B with appropriate MultiSynth configuration and input reference.
Does SI5334C-B04088-GM support spread spectrum clocking (SSC)?
Yes, SI5334C-B04088-GM supports PCIe 2.0–compliant spread spectrum on any output clock running at exactly 100 MHz, provided the Rn divider is set to 1. The modulation is ±0.5% deviation at 30–33 kHz and is enabled per-output via factory programming - no pin control or runtime configuration is required once programmed.
Can SI5334C-B04088-GM generate different output formats simultaneously?
Yes, SI5334C-B04088-GM supports simultaneous mixed-format outputs: for example, CLK0A/B as LVPECL (156.25 MHz), CLK1A/B as LVDS (125 MHz), CLK2A/B as HCSL (100 MHz), and CLK3A/B as CMOS (25 MHz). Each output has independent VDDO and format selection, enabling direct interfacing with diverse logic families without external level shifters.
Is SI5334C-B04088-GM pin-compatible with other Si5334 variants?
Yes, all Si5334 variants - including SI5334C-B04088-GM - share identical 24-QFN pinout, electrical characteristics, and functional block diagram. Differences are limited to factory-programmed configuration (frequency plan, output format, voltage, SSC enable), meaning PCB layout and schematic symbols are fully reusable across the Si5334 family.
What reference inputs does SI5334C-B04088-GM accept?
SI5334C-B04088-GM accepts multiple reference types: 8–30 MHz fundamental-mode crystals (differential), or single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) clock inputs. Input pins IN1/IN2 and IN5/IN6 are AC-coupled differential; IN3/IN4 are DC-coupled single-ended with internal biasing - no external resistors needed.
SI5334C-B04088-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5334C-B04088-GM FAQ
1.How can I place an order for SI5334C-B04088-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5334C-B04088-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5334C-B04088-GM reliable?
The price and inventory of SI5334C-B04088-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B04088-GM is usually 5 days.
3.What payment methods are accepted for SI5334C-B04088-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B04088-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5334C-B04088-GM?
SI5334C-B04088-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5334C-B04088-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5334C-B04088-GM?
For technical support, including SI5334C-B04088-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B04088-GM requirements.
6.How does Aetrix verify that SI5334C-B04088-GM is sourced from the original manufacturer or authorized distributors?
All SI5334C-B04088-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B04088-GM meets industry standards.
7.What is the process for return or replacement of SI5334C-B04088-GM?
All SI5334C-B04088-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B04088-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5334C-B04088-GM part is unused and in its original packaging.
Return procedure for SI5334C-B04088-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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