Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334C-B04104-GMR

Name: SI5334C-B04104-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5334C-B04104-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5334C-B04104-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334C-B04104-GMR.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,857

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5334C-B04104-GMR from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator IC with four independently configurable differential clock outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz per output using MultiSynth fractional-N PLL technology, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, and operates from 1.8/2.5/3.3 V core and output supply rails. It is deployed in PCIe 3.0 timing, FPGA clocking, and broadcast video systems.

For engineers reviewing the SI5334C-B04104-GMR datasheet, SI5334C-B04104-GMR pinout, SI5334C-B04104-GMR application, or SI5334C-B04104-GMR equivalent, this page provides verified specifications, validated pin functions, confirmed use cases in telecom line cards and 10 GbE systems, and two field-validated alternative parts with documented technical and application differences.

Technical Context

The SI5334C-B04104-GMR integrates a single high-stability fractional-N PLL with four independent MultiSynth output dividers, enabling zero-ppm frequency synthesis across all four outputs. Its input stage accepts crystal (8–30 MHz) or differential/single-ended clocks up to 710 MHz, and its synthesis stage supports integer and fractional modes with <1 ppb resolution.

Each output driver features independent voltage control (1.5/1.8/2.5/3.3 V), selectable signal format, and programmable phase offset (±45 ns in 20 ps steps). The device implements pin-controlled frequency increment/decrement (1 ppm steps, glitchless) on CLK0A/B only and supports PCI Express–compliant spread spectrum on 100 MHz outputs.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B through CLK3A/B), each independently configurable
Frequency range per output	0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS with specific divider settings
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), enabling compliance with PCIe 3.0 and 10 GbE jitter budgets
Core supply voltage	1.8 V, 2.5 V, or 3.3 V ±10%, supporting mixed-voltage system integration
Output voltage flexibility	Independent VDDOx per output (1.4–3.63 V), allowing mixed-signal interface to FPGAs, ASICs, and SerDes
Input reference options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz)
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, with exposed thermal pad

Pinout & Package

SI5334C-B04104-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin numbering follows standard QFN top-view convention (pin 1 at top-left corner, counterclockwise).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts AC-coupled 5–710 MHz differential clock; internal 10 kΩ termination enables direct connection to LVDS/HCSL sources
IN3 / IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL clocks (5–350 MHz); VIH/VIL thresholds scale with VDD for robust level translation
CLK0A / CLK0B through CLK3A / CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL with dedicated VDDOx supply
VDDO0–VDDO3	Output buffer supply rails	Enable per-output voltage selection (1.4–3.63 V) to match connected logic families without external level shifters
VDD	Core supply	Supplies PLL, MultiSynth, and control logic; supports 1.8/2.5/3.3 V operation with <60 mA max current draw
LOSLOL	Loss-of-signal/loss-of-lock alarm output	Open-drain active-low flag indicating input failure or PLL unlock; drives external monitoring circuitry or MCU GPIO
OEB	Output enable/disable control	Active-low pin that disables all output drivers simultaneously to reduce EMI during power-down or standby
RSVD_GND	Reserved ground terminal	Internally connected to die substrate; must be tied to PCB ground plane for thermal and noise integrity

Key Features

Feature	Design Value
MultiSynth fractional-N synthesis	Enables any-frequency generation (0.16–710 MHz) on all four outputs with zero ppm error and <1 ppb resolution
Per-output voltage and format control	Eliminates need for external level translators by supporting mixed-voltage designs (e.g., 1.8 V FPGA + 3.3 V PHY)
Pin-controlled frequency adjustment	Glitchless 1 ppm step increments/decrements on CLK0A/B for margin testing and dynamic frequency tuning
Programmable phase offset	±45 ns adjustment in 20 ps steps per output, enabling precise skew management in multi-lane SerDes interfaces
PCIe-compliant spread spectrum	Reduces EMI on 100 MHz outputs without violating PCIe 2.0/3.0 jitter masks or requiring host software control

Applications

Ethernet Switch/Routing	PCI Express 3.0 Timing
Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronous clocking across multiple MAC/PHY layers and packet buffers. IC Role / Device Role / Timing Role: Primary clock generator providing four low-jitter, independently timed reference clocks for SERDES lanes, switch fabric, and control processors. Use Value: 0.7 ps RMS jitter ensures PCIe 3.0 and IEEE 802.3ae compliance; pin-controlled frequency margining validates timing closure under voltage/temperature corners.	Use Scenario: Server motherboard with multiple PCIe 3.0 slots, NVMe SSDs, and root complex, demanding strict common-clock jitter alignment. IC Role / Device Role / Timing Role: Common-clock source delivering synchronized 100 MHz HCSL clocks to all PCIe endpoints with matched phase and SSC capability. Use Value: Spread spectrum on 100 MHz outputs reduces EMI without violating PCIe 3.0 total jitter limit of 3.0 ps RMS; zero-ppm accuracy prevents link training failures.
Broadcast Video Timing	FPGA & Processor Clocking
Use Scenario: SMPTE ST 2082/ST 2110 IP video router requiring genlock-capable, frame-accurate clock distribution across 4K/8K processing pipelines. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from a single 25 MHz crystal reference. Use Value: Independent MultiSynth dividers allow simultaneous generation of non-integer-related video rates; phase adjustment aligns pixel clock edges across parallel processing paths.	Use Scenario: Industrial FPGA-based motion controller needing separate clocks for ARM processor core, DDR3 memory interface, and real-time I/O peripherals. IC Role / Device Role / Timing Role: Quad-output clock source supplying 100 MHz (ARM), 400 MHz (DDR3), 50 MHz (UART), and 125 MHz (GigE MAC) from one device. Use Value: Per-output VDDOx rails eliminate level-shifter components; 1.8 V core supply reduces power in space-constrained embedded modules.

Ethernet Switch/Routing

PCI Express 3.0 Timing

Use Scenario: High-density 10 GbE/25 GbE switch fabric requiring synchronous clocking across multiple MAC/PHY layers and packet buffers.

IC Role / Device Role / Timing Role: Primary clock generator providing four low-jitter, independently timed reference clocks for SERDES lanes, switch fabric, and control processors.

Use Value: 0.7 ps RMS jitter ensures PCIe 3.0 and IEEE 802.3ae compliance; pin-controlled frequency margining validates timing closure under voltage/temperature corners.

Use Scenario: Server motherboard with multiple PCIe 3.0 slots, NVMe SSDs, and root complex, demanding strict common-clock jitter alignment.

IC Role / Device Role / Timing Role: Common-clock source delivering synchronized 100 MHz HCSL clocks to all PCIe endpoints with matched phase and SSC capability.

Use Value: Spread spectrum on 100 MHz outputs reduces EMI without violating PCIe 3.0 total jitter limit of 3.0 ps RMS; zero-ppm accuracy prevents link training failures.

Broadcast Video Timing

FPGA & Processor Clocking

Use Scenario: SMPTE ST 2082/ST 2110 IP video router requiring genlock-capable, frame-accurate clock distribution across 4K/8K processing pipelines.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer generating 27 MHz, 74.25 MHz, and 148.5 MHz video clocks from a single 25 MHz crystal reference.

Use Value: Independent MultiSynth dividers allow simultaneous generation of non-integer-related video rates; phase adjustment aligns pixel clock edges across parallel processing paths.

Use Scenario: Industrial FPGA-based motion controller needing separate clocks for ARM processor core, DDR3 memory interface, and real-time I/O peripherals.

IC Role / Device Role / Timing Role: Quad-output clock source supplying 100 MHz (ARM), 400 MHz (DDR3), 50 MHz (UART), and 125 MHz (GigE MAC) from one device.

Use Value: Per-output VDDOx rails eliminate level-shifter components; 1.8 V core supply reduces power in space-constrained embedded modules.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05104-GM	Higher integration: 8 outputs, integrated EEPROM, I²C programmability; 0.5 ps RMS jitter; 4×4 mm QFN-32	Requires firmware initialization and I²C bus; better suited for dynamic reconfiguration, not pin-control-only systems	Select when field-upgradable configuration or >4 outputs are required; not drop-in due to pin count, package, and control interface mismatch
ICS853S02IAGLF	Fixed-frequency dual-output LVDS generator; 1.2 ps RMS jitter; 3.3 V only; no frequency synthesis or format flexibility	Limited to pre-programmed 100/125 MHz outputs; no phase/frequency adjustment or multi-format support	Select only for cost-sensitive, fixed-rate applications where synthesis flexibility and low jitter are secondary to BOM simplicity

Compared with SI5334C-B04104-GMR, Si5332A-D05104-GM adds programmability and output count at the cost of pin-control simplicity and layout compatibility, while ICS853S02IAGLF trades synthesis capability for lower unit cost and guaranteed fixed-frequency stability.

Availability

SI5334C-B04104-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe 3.0 timing, and broadcast video timing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for SI5334C-B04104-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and industrial markets.

The Si5334 family is designed as a pin-configurable, any-frequency quad clock generator targeting high-speed serial interface timing in networking, computing, and video infrastructure equipment.

FAQ

What is the maximum output frequency supported by SI5334C-B04104-GMR?

The SI5334C-B04104-GMR supports up to 710 MHz on LVPECL and LVDS outputs when operating in specific MultiSynth fractional mode configurations with appropriate R-divider settings. For all output formats and guaranteed performance across temperature and voltage, the maximum is 350 MHz. Frequencies above 350 MHz require validation per AN562 and are limited to two unique outputs simultaneously above Fvco/8.

Does SI5334C-B04104-GMR support crystal input?

Yes, SI5334C-B04104-GMR supports fundamental-mode crystals from 8 MHz to 30 MHz directly connected to IN1/IN2 pins. The device includes on-chip load capacitance (11–13 pF supported, 17–19 pF recommended) and automatic crystal drive level control to ensure reliable start-up and low phase noise.

Can SI5334C-B04104-GMR generate different output formats simultaneously?

Yes, SI5334C-B04104-GMR allows independent configuration of each of its four differential output pairs (CLK0A/B through CLK3A/B) for LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL formats. Each output has its own VDDOx supply rail, enabling concurrent operation with mixed logic families on a single board.

What is the function of the LOSLOL pin on SI5334C-B04104-GMR?

The LOSLOL pin on SI5334C-B04104-GMR is an open-drain, active-low alarm output that asserts when either loss-of-signal (on any enabled input) or loss-of-lock (PLL unlocked) is detected. It deasserts within 0.2–1 µs after recovery and can drive external monitoring circuitry or microcontroller interrupt lines without pull-up resistors beyond 1 kΩ.

Is SI5334C-B04104-GMR compatible with PCIe 3.0 jitter requirements?

Yes, SI5334C-B04104-GMR meets PCIe 3.0 jitter requirements with 0.15–0.45 ps RMS (10 kHz–50 MHz) measured on 100 MHz HCSL outputs. Its 0.7 ps RMS typical phase jitter and deterministic jitter <10 ps pk-pk in integer mode ensure compliance with PCIe 3.0 common clock architecture specifications.

SI5334C-B04104-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334C-B04104-GMR FAQ

1.How can I place an order for SI5334C-B04104-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334C-B04104-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334C-B04104-GMR reliable?

The price and inventory of SI5334C-B04104-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B04104-GMR is usually 5 days.

3.What payment methods are accepted for SI5334C-B04104-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B04104-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334C-B04104-GMR?

SI5334C-B04104-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334C-B04104-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334C-B04104-GMR?

For technical support, including SI5334C-B04104-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B04104-GMR requirements.

6.How does Aetrix verify that SI5334C-B04104-GMR is sourced from the original manufacturer or authorized distributors?

All SI5334C-B04104-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B04104-GMR meets industry standards.

7.What is the process for return or replacement of SI5334C-B04104-GMR?

All SI5334C-B04104-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B04104-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334C-B04104-GMR part is unused and in its original packaging.

Return procedure for SI5334C-B04104-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…