Skyworks Solutions Inc. SI5334C-B04195-GM
- Part No.:
- SI5334C-B04195-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5334C-B04195-GM.pdf
- Description:
- 4-OUTPUT, ANY FREQUENCY(<200MHZ)
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5334C-B04195-GM from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs, 0.7 ps RMS typical phase jitter, 0 ppm frequency accuracy, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats up to 710 MHz - deployed in Ethernet switches, PCIe 3.0 systems, and FPGA clocking.
For engineers reviewing the SI5334C-B04195-GM datasheet, SI5334C-B04195-GM pinout, SI5334C-B04195-GM application, or SI5334C-B04195-GM equivalent, key selection considerations include its 24-pin 4×4 mm QFN package, factory-programmed configuration, 1.8/2.5/3.3 V core supply flexibility, independent output voltage per driver (1.5–3.3 V), and MultiSynth-based zero-ppm synthesis across all outputs.
Technical Context
The SI5334C-B04195-GM integrates a fractional-N PLL with on-chip VCO and four independent MultiSynth dividers, enabling integer or fractional frequency synthesis on each of four differential outputs. Input reference options include 8–30 MHz crystal or 5–710 MHz differential/single-ended clocks.
Each output supports programmable phase offset (±45 ns, <20 ps step), glitchless frequency increment/decrement (1 ppm steps, up to 350 MHz), and optional PCIe-compliant spread spectrum on 100 MHz outputs. Loss-of-lock and loss-of-signal detection are implemented via dedicated LOSLOL pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential clock outputs (CLK0A/B through CLK3A/B), each independently configurable |
| Frequency range | 0.16–710 MHz per output; 350 MHz guaranteed for any frequency, select frequencies to 710 MHz |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz); meets PCIe 3.0, GbE, OC-12 timing requirements |
| Frequency accuracy | True 0 ppm error on all outputs via MultiSynth fractional synthesis |
| Supply voltages | Core: 1.8 / 2.5 / 3.3 V; Output buffers: 1.5 / 1.8 / 2.5 / 3.3 V, independently assignable per driver |
| Input reference | Crystal (8–30 MHz) or AC/DC-coupled clock (5–710 MHz differential, 5–350 MHz single-ended) |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad |
Pinout & Package
SI5334C-B04195-GM is housed in a 24-lead, 4×4 mm QFN package with exposed thermal pad (pin 24 = GND). Pin assignments follow Skyworks' standard Si5334 top-view layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1 / IN2 | Differential reference input (P/N) | Accepts 5–710 MHz AC-coupled differential clock; internal 10 kΩ termination |
| IN3 / IN4 | Single-ended reference input (P/N) | Accepts 5–200 MHz CMOS/SSTL/HSTL; 20 kΩ pull-up/pull-down configurable |
| IN5 / IN6 | Differential feedback input (P/N) | Enables zero-delay mode when routed from CLKx output; supports FDBKSE mode |
| CLK0A / CLK0B through CLK3A / CLK3B | Differential clock outputs (4 pairs) | Each pair supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL; individually voltage- and format-configurable |
| VDDO0–VDDO3 | Output buffer supply pins (4) | Independent 1.5–3.3 V supplies per output pair; enables mixed-voltage system interfacing |
| VDD | Core supply | 1.8 / 2.5 / 3.3 V ±10%; powers PLL, MultiSynth, control logic |
| LOSLOL | Loss-of-signal/loss-of-lock alarm | Open-drain active-low output; asserts within 5 µs of input failure or PLL unlock |
| OEB | Output enable / blank | Active-low control; disables all outputs simultaneously without affecting internal state |
| RSVD_GND | Reserved ground | Internally connected to die substrate; must be tied to PCB ground plane |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth frequency synthesis | Zero-ppm accuracy on all four outputs with sub-Hz resolution; eliminates need for multiple crystals or external synthesizers |
| Independent output configuration | Each of four differential outputs supports independent signal format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), and frequency (0.16–710 MHz) |
| Glitchless frequency tuning | Pin-controlled frequency increment/decrement at 1 ppm steps, up to 350 MHz, enabling margin testing and dynamic clock adaptation |
| Programmable phase alignment | ±45 ns phase offset per output with <20 ps step resolution, supporting precise timing skew compensation in multi-lane interfaces |
| PCIe-compliant spread spectrum | SSC enabled on any 100 MHz output with –0.5% deviation at 30–33 kHz; reduces EMI without violating PCIe 2.0/3.0 jitter limits |
| Zero-delay mode support | External feedback path via IN5/IN6 enables phase-locked output-to-input tracking for clock forwarding applications |
Applications
| Ethernet Switch/Routing | PCI Express 3.0 System Clocking |
|---|---|
Use Scenario: Synchronizing packet processing, MAC layer timing, and SerDes lanes in 1/10 GbE switch fabric ASICs. IC Role / Device Role / Timing Role: Primary clock source generating independent 125 MHz, 156.25 MHz, and 250 MHz clocks for PHY, MAC, and CPU subsystems. Use Value: 0.7 ps RMS jitter ensures compliance with IEEE 802.3ae jitter budgets; independent output voltage control simplifies interface to mixed-supply SoCs. |
Use Scenario: Providing reference clocks to PCIe root complex, endpoint devices, and switch ICs in server/storage platforms. IC Role / Device Role / Timing Role: Generating 100 MHz differential HCSL clocks with PCIe 3.0-compliant jitter (<0.45 ps RMS) and optional SSC for EMI reduction. Use Value: Factory-programmed configuration eliminates I²C initialization overhead; zero-ppm synthesis avoids link training failures due to frequency drift. |
| FPGA & Processor Clocking | Broadcast Video Timing |
Use Scenario: Delivering multiple synchronized clocks to high-end FPGAs (e.g., Xilinx Versal, Intel Stratix) for logic, transceivers, and memory interfaces. IC Role / Device Role / Timing Role: Synthesizing 100 MHz, 161.1328125 MHz (CPRI), and 297 MHz (HDMI 2.1) from a single 25 MHz crystal reference. Use Value: Four independent MultiSynth engines eliminate need for discrete clock buffers or synthesizers; phase adjustment aligns setup/hold margins across clock domains. |
Use Scenario: Generating SMPTE ST 2059-2–compliant PTP grandmaster clocks and genlock signals for 4K/8K video encoders, routers, and IP media gateways. IC Role / Device Role / Timing Role: Producing 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with ultra-low deterministic jitter (<10 ps pk-pk) for pixel-accurate sampling. Use Value: Sub-20 ps phase step resolution enables frame-accurate synchronization across distributed video processing nodes; 1.8 V core supply supports low-power broadcast edge hardware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D08189-GM | 8-output, higher integration; includes integrated EEPROM and I²C interface; lower jitter (0.35 ps RMS) | Requires firmware initialization; better suited for dynamically reconfigurable systems | Select when design requires field-updatable configurations or >4 outputs; not pin-compatible |
| ICS8430I-01T | 4-output, fixed-frequency; no any-frequency synthesis; 1.2 ps RMS jitter; 3.3 V only | Limited to pre-defined frequency plans; no phase/frequency tuning capability | Select for cost-sensitive, static-clock applications where MultiSynth flexibility is unnecessary |
Compared with Si5332A-D08189-GM and ICS8430I-01T, SI5334C-B04195-GM delivers unique value in pin-controlled, factory-programmed any-frequency generation with zero-ppm accuracy and minimal BOM overhead - ideal for volume production of PCIe, Ethernet, and FPGA-based systems requiring deterministic timing without software intervention.
Availability
SI5334C-B04195-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe 3.0 host controller, and FPGA clocking applications requiring stable component supply, long-term lifecycle assurance, and full traceability.
Supply support for SI5334C-B04195-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and industrial markets.
The Si5334 family was designed to replace multiple discrete clock sources with a single, highly flexible, low-jitter clock generator for high-speed serial interface timing - targeting PCIe, Ethernet, and broadcast video systems demanding zero-ppm accuracy and minimal board space.
FAQ
What is the factory-programmed configuration of SI5334C-B04195-GM?
The SI5334C-B04195-GM is pre-programmed by Skyworks with a specific frequency plan, output formats, and voltage settings defined at order time. It operates immediately upon power-up without I²C initialization. Configuration details - including exact output frequencies and signal formats - are documented in the custom datasheet provided with the part number SI5334C-B04195-GM and verified via Skyworks' ClockBuilder Pro tool.
Does SI5334C-B04195-GM support spread spectrum clocking (SSC)?
Yes, SI5334C-B04195-GM supports PCIe-compliant spread spectrum on any output clock operating at exactly 100 MHz with Rn divider set to 1. The modulation rate is 30–33 kHz with ±0.5% frequency deviation - meeting PCIe 2.0/3.0 EMI requirements while maintaining jitter below 0.45 ps RMS. SSC is disabled by default and enabled via factory programming of SI5334C-B04195-GM.
Can SI5334C-B04195-GM generate 710 MHz outputs?
Yes, SI5334C-B04195-GM can generate 710 MHz outputs, but only on LVPECL or CML output formats and only when the MultiSynth output frequency falls within the Fvco/4 or Fvco/6 bands. This capability is limited to two unique frequencies above Fvco/8 simultaneously. Full 710 MHz operation requires proper layout, termination, and power integrity - confirmed in the SI5334C-B04195-GM datasheet's "Output Clock Characteristics" table.
What is the function of the LOSLOL pin on SI5334C-B04195-GM?
The LOSLOL pin on SI5334C-B04195-GM is an open-drain, active-low alarm that asserts within 2.6–5 µs of input clock loss or PLL loss-of-lock. It monitors both reference input (IN1–IN6) and internal PLL status. When asserted, it signals system-level fault detection logic to initiate failover or diagnostic routines - a critical feature for high-availability Ethernet and telecom line card designs using SI5334C-B04195-GM.
Is SI5334C-B04195-GM pin-compatible with other Si5334 variants?
Yes, all Si5334 variants - including SI5334C-B04195-GM - share identical 24-pin QFN packaging, pinout, and footprint. Differences lie solely in factory-programmed configuration (frequencies, formats, voltages) and internal OTP content. No PCB redesign is required when migrating between Si5334 part numbers, provided thermal and decoupling design guidelines for the 4×4 mm QFN package are followed for SI5334C-B04195-GM.
SI5334C-B04195-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5334C-B04195-GM FAQ
1.How can I place an order for SI5334C-B04195-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5334C-B04195-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5334C-B04195-GM reliable?
The price and inventory of SI5334C-B04195-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B04195-GM is usually 5 days.
3.What payment methods are accepted for SI5334C-B04195-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B04195-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5334C-B04195-GM?
SI5334C-B04195-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5334C-B04195-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5334C-B04195-GM?
For technical support, including SI5334C-B04195-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B04195-GM requirements.
6.How does Aetrix verify that SI5334C-B04195-GM is sourced from the original manufacturer or authorized distributors?
All SI5334C-B04195-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B04195-GM meets industry standards.
7.What is the process for return or replacement of SI5334C-B04195-GM?
All SI5334C-B04195-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B04195-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5334C-B04195-GM part is unused and in its original packaging.
Return procedure for SI5334C-B04195-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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