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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334C-B04811-GM

Name: SI5334C-B04811-GM
Brand: Skyworks Solutions Inc.
SKU: SI5334C-B04811-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334C-B04811-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334C-B04811-GM.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334C-B04811-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, supporting frequencies up to 350 MHz (and select outputs to 710 MHz), 0.7 ps RMS typical phase jitter, and zero ppm frequency error via MultiSynth synthesis. It operates from 1.8/2.5/3.3 V core supply and targets high-precision timing in PCIe 3.0, Ethernet switch/router, and FPGA clocking systems.

For engineers reviewing the SI5334C-B04811-GM datasheet, SI5334C-B04811-GM pinout, SI5334C-B04811-GM application, or SI5334C-B04811-GM equivalent, this device delivers factory-programmed, glitchless frequency/phase adjustment, flexible input reference support (crystal, CMOS, SSTL, differential), and per-output voltage control (1.5–3.3 V) - critical for mixed-signal timing integrity in telecom and datacom designs.

Technical Context

The SI5334C-B04811-GM implements a fractional-N PLL architecture with integrated VCO and four independent MultiSynth output dividers, enabling non-integer frequency synthesis on each of its four differential outputs. Its input stage accepts 8–30 MHz crystals or 5–710 MHz clock inputs across multiple logic families (CMOS, SSTL/HSTL, differential).

Each output driver supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats with independent VDDO supply (1.5–3.3 V), and features pin-controlled phase increment/decrement (±45 ns range, 20 ps step) and frequency increment/decrement (1 ppm steps, glitchless) on CLK0A/B. Loss-of-lock and loss-of-signal detection are provided via LOSLOL pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B), each independently configurable
Frequency Range	0.16–350 MHz standard; select outputs support 367–710 MHz - enables multi-rate system clocking without external dividers
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz); meets PCIe 3.0 and 10GbE jitter requirements
Frequency Accuracy	True 0 ppm error across all outputs - eliminates need for calibration or trimming in production
Core Supply Voltage	1.8 V, 2.5 V, or 3.3 V - supports mixed-voltage board architectures with single-device integration
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 mm × 4 mm - space-constrained PCB layouts in dense switch/router modules

Pinout & Package

SI5334C-B04811-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standardized Si5334 pinout, including dedicated differential input pairs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B through CLK3A/B), independent VDDO supplies (VDDO0–VDDO3), core supply (VDD), control pins (OEB, LOSLOL), and reserved ground (RSVD_GND).

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A / CLK0B	Differential output pair 0	Factory-configured primary output; supports frequency/phase adjustment via PINC/FINC pins
CLK1A / CLK1B	Differential output pair 1	Independent synthesis path; format and voltage (VDDO1) configurable per application
VDDO0–VDDO3	Output buffer supply pins	Enable per-output voltage selection (1.5/1.8/2.5/3.3 V) for mixed-interface systems
OEB	Output enable / blanking control	Active-low; disables all outputs simultaneously for power sequencing or test mode
LOSLOL	Loss-of-signal / loss-of-lock indicator	Open-drain output asserts low on input failure or PLL unlock; tLOS = 2.6–5 µs response

Key Features

Feature	Design Value
MultiSynth frequency synthesis	Enables any-frequency generation (0.16–350 MHz) on all four outputs with zero ppm error and <0.7 ps RMS jitter
Per-output signal format selection	LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL per channel - eliminates level-shifting components
Independent output voltage control	VDDO0–VDDO3 allow 1.5/1.8/2.5/3.3 V per driver - supports mixed-supply FPGAs and ASICs
Glitchless frequency tuning	1 ppm step size, ±350 MHz range on CLK0A/B - enables margin testing and dynamic frequency scaling
Sub-20 ps phase adjustment	±45 ns range in 20 ps increments per output - precise skew management for SerDes alignment
PCIe-compliant spread spectrum	SSC available on 100 MHz outputs with –0.5% deviation at 30–33 kHz - reduces EMI without violating spec

Applications

Ethernet Switch/Router Timing	PCI Express 3.0 Clocking
Use Scenario: Synchronizing 10GbE MACs, packet buffers, and switching fabric in Layer 3 routers with strict jitter budgets. IC Role / Device Role / Timing Role: Primary clock generator delivering four low-jitter clocks (125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz) to PHYs and switch ASICs. Use Value: 0.7 ps RMS jitter ensures compliance with IEEE 802.3ae and PCIe 3.0 jitter masks, reducing bit error rates and link training failures.	Use Scenario: Providing reference clocks to root complex, endpoint, and switch devices in PCIe 3.0 add-in cards and server backplanes. IC Role / Device Role / Timing Role: Generating 100 MHz SSC-enabled and non-SSC clocks with matched phase alignment across lanes. Use Value: Built-in PCIe-compliant spread spectrum on 100 MHz outputs eliminates need for external modulation circuitry while maintaining <0.45 ps RMS jitter.
FPGA & Processor Clock Distribution	Broadcast Video/Audio Timing
Use Scenario: Feeding multiple clock domains (fabric, I/O, transceivers, DDR interfaces) in Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Quad-output generator supplying 100 MHz, 200 MHz, 300 MHz, and 400 MHz clocks with independent voltage and format control. Use Value: Per-output VDDO (1.5–3.3 V) and LVDS/HCSL/CMOS format flexibility eliminate discrete level shifters and reduce BOM count.	Use Scenario: Master timing source for SMPTE ST 2082 (12G-SDI), AES67 audio-over-IP, and video processing pipelines. IC Role / Device Role / Timing Role: Delivering synchronized 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with sub-1 ps RMS jitter to ADCs, DACs, and serializers. Use Value: 0.7 ps RMS jitter and <10 ps cycle-cycle jitter preserve eye diagram integrity in 12G-SDI serial links, preventing pixel errors and frame drops.

Ethernet Switch/Router Timing

PCI Express 3.0 Clocking

Use Scenario: Synchronizing 10GbE MACs, packet buffers, and switching fabric in Layer 3 routers with strict jitter budgets.

IC Role / Device Role / Timing Role: Primary clock generator delivering four low-jitter clocks (125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz) to PHYs and switch ASICs.

Use Value: 0.7 ps RMS jitter ensures compliance with IEEE 802.3ae and PCIe 3.0 jitter masks, reducing bit error rates and link training failures.

Use Scenario: Providing reference clocks to root complex, endpoint, and switch devices in PCIe 3.0 add-in cards and server backplanes.

IC Role / Device Role / Timing Role: Generating 100 MHz SSC-enabled and non-SSC clocks with matched phase alignment across lanes.

Use Value: Built-in PCIe-compliant spread spectrum on 100 MHz outputs eliminates need for external modulation circuitry while maintaining <0.45 ps RMS jitter.

FPGA & Processor Clock Distribution

Broadcast Video/Audio Timing

Use Scenario: Feeding multiple clock domains (fabric, I/O, transceivers, DDR interfaces) in Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Quad-output generator supplying 100 MHz, 200 MHz, 300 MHz, and 400 MHz clocks with independent voltage and format control.

Use Value: Per-output VDDO (1.5–3.3 V) and LVDS/HCSL/CMOS format flexibility eliminate discrete level shifters and reduce BOM count.

Use Scenario: Master timing source for SMPTE ST 2082 (12G-SDI), AES67 audio-over-IP, and video processing pipelines.

IC Role / Device Role / Timing Role: Delivering synchronized 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with sub-1 ps RMS jitter to ADCs, DACs, and serializers.

Use Value: 0.7 ps RMS jitter and <10 ps cycle-cycle jitter preserve eye diagram integrity in 12G-SDI serial links, preventing pixel errors and frame drops.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05889-GM	Higher integration: 8 outputs, integrated EEPROM, I²C programmability; 0.5 ps RMS jitter; supports JESD204B deterministic latency	Targeted at JESD204B-based RF/data converter systems requiring deterministic delay control	Choose when field reconfiguration, higher output count, or deterministic latency is required - not pin-compatible
ICS8430I-01T	4-output LVDS-only generator; 1.2 ps RMS jitter; fixed 100/125/156.25 MHz outputs; no frequency/phase tuning	Suitable for cost-sensitive, fixed-frequency applications like basic Ethernet PHY clocking	Choose for simple, low-cost replacement where programmability and jitter headroom are not critical

Compared with SI5334C-B04811-GM, Si5332A-D05889-GM adds I²C configurability and lower jitter but increases complexity and cost, while ICS8430I-01T offers simplicity and lower price at the expense of flexibility and performance - making SI5334C-B04811-GM optimal for balanced programmability, jitter, and footprint in mid-tier datacom designs.

Availability

SI5334C-B04811-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe 3.0 add-in cards, and broadcast video timing applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5334C-B04811-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and mobile markets.

The Si5334 family is designed for high-performance, any-frequency clock generation in datacom, telecom, and broadcast equipment - emphasizing low jitter, pin-control simplicity, and multi-format output flexibility without requiring microcontroller intervention.

FAQ

What is the maximum output frequency supported by SI5334C-B04811-GM?

The SI5334C-B04811-GM supports up to 350 MHz on all four differential outputs under standard operation. Select outputs can be configured to 367–473.33 MHz or 550–710 MHz depending on MultiSynth division ratios and VCO constraints - verified in Table 4 of the official datasheet. Frequencies above 350 MHz require specific configuration and are not guaranteed across all operating conditions.

Does SI5334C-B04811-GM support crystal input?

Yes, SI5334C-B04811-GM supports direct connection of an 8–30 MHz fundamental-mode crystal to IN1/IN2 pins. The device provides on-chip load capacitance options (11–13 pF supported, 17–19 pF recommended) and internal oscillator circuitry - no external capacitors or buffer ICs are required for basic crystal operation.

Can SI5334C-B04811-GM generate different output formats simultaneously?

Yes, SI5334C-B04811-GM allows independent configuration of each output pair (CLK0A/B through CLK3A/B) for LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL formats. This enables simultaneous delivery of, for example, LVDS to an FPGA bank and HCSL to a CPU - confirmed in Section 2.5 and Table 4 of the datasheet.

Is SI5334C-B04811-GM pin-compatible with other Si5334 variants?

Yes, all Si5334 variants - including SI5334C-B04811-GM - share identical 24-QFN pinout, electrical characteristics, and functional block diagram. Differences are limited to factory-programmed configuration (frequency plan, output format, voltage, and feature enablement), not physical or logical interface.

What is the purpose of the LOSLOL pin on SI5334C-B04811-GM?

The LOSLOL pin on SI5334C-B04811-GM is an open-drain indicator that asserts low within 2.6–5 µs upon loss of input signal (on IN1/IN2 or IN3/IN4) or loss of PLL lock. It serves as a hardware fault flag for system monitoring and fail-safe shutdown - detailed in Section 2.12 and Table 5 of the datasheet.

SI5334C-B04811-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334C-B04811-GM FAQ

1.How can I place an order for SI5334C-B04811-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334C-B04811-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334C-B04811-GM reliable?

The price and inventory of SI5334C-B04811-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B04811-GM is usually 5 days.

3.What payment methods are accepted for SI5334C-B04811-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B04811-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334C-B04811-GM?

SI5334C-B04811-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334C-B04811-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334C-B04811-GM?

For technical support, including SI5334C-B04811-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B04811-GM requirements.

6.How does Aetrix verify that SI5334C-B04811-GM is sourced from the original manufacturer or authorized distributors?

All SI5334C-B04811-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B04811-GM meets industry standards.

7.What is the process for return or replacement of SI5334C-B04811-GM?

All SI5334C-B04811-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B04811-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334C-B04811-GM part is unused and in its original packaging.

Return procedure for SI5334C-B04811-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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