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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334C-B05192-GM

Name: SI5334C-B05192-GM
Brand: Skyworks Solutions Inc.
SKU: SI5334C-B05192-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334C-B05192-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334C-B05192-GM.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334C-B05192-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, 0 ppm frequency accuracy, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats up to 710 MHz - deployed in Ethernet switch timing, PCIe 3.0 clocking, and FPGA synchronization.

For engineers reviewing the SI5334C-B05192-GM datasheet, SI5334C-B05192-GM pinout, SI5334C-B05192-GM application, or SI5334C-B05192-GM equivalent, this page delivers verified specifications including MultiSynth-based fractional-N synthesis, 4×4 mm 24-QFN package, independent output voltage per driver (1.5–3.3 V), loss-of-lock detection, and glitchless 1 ppm frequency increment/decrement on CLK0A/B.

Technical Context

The SI5334C-B05192-GM integrates a fully on-chip fractional-N PLL with phase detector, charge pump, loop filter, VCO, and R/M/N dividers, enabling integer or fractional synthesis per output. Its dual-stage architecture separates input reference conditioning (Stage 1) from per-output MultiSynth synthesis (Stage 2), supporting independent frequency, format, and voltage configuration per channel.

Each of the four differential output pairs (CLK0A/B through CLK3A/B) features dedicated output drivers with programmable signal format, independent VDDO supply (1.5/1.8/2.5/3.3 V), and <20 ps phase step resolution over ±45 ns range. Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B), each independently configurable
Frequency range	0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS with specific divider settings
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), validated for 125 MHz GbE and 155.52 MHz OC-12 applications
Frequency accuracy	True 0 ppm error across all outputs due to MultiSynth fractional synthesis without rounding
Supply voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments

Pinout & Package

SI5334C-B05192-GM is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments are fixed per Skyworks Si5334 family layout and match the transparent top view shown in the official datasheet Rev. 1.3.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts AC-coupled 5–710 MHz differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference inputs	Support CMOS/SSTL/HSTL clocks (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A / CLK0B	Differential output pair 0	Primary output with full frequency/phase/frequency increment-decrement capability
CLK1A / CLK1B	Differential output pair 1	Fully independent synthesis path; supports same format/voltage/frequency ranges as CLK0
CLK2A / CLK2B	Differential output pair 2	Configurable for any supported format; no frequency inc/dec control (pin-strapped variant)
CLK3A / CLK3B	Differential output pair 3	Independent output with full format and voltage selection; used for secondary system clocks
VDDO0–VDDO3	Output buffer supply pins	Each powers one output pair; enables mixed-voltage operation (e.g., 1.8 V LVDS + 3.3 V CMOS)
VDD	Core supply	Supplies PLL, MultiSynth logic, and control circuitry; accepts 1.8/2.5/3.3 V ±10%
LOSLOL	Loss-of-signal/loss-of-lock open-drain alarm	Asserts low on input failure or PLL unlock; sinks 3 mA, compatible with 1 kΩ pull-up
OEB	Output enable (active-low)	Global disable for all four output pairs; high-Z state preserves signal integrity during standby

Key Features

Feature	Design Value
MultiSynth fractional-N synthesis	Enables zero-ppm frequency accuracy on all four outputs without external VCXO or loop filter components
Independent output voltage per driver	Allows simultaneous LVDS (1.8 V) and HCSL (3.3 V) outputs on same device, eliminating level-shifter ICs
Glitchless frequency increment/decrement	1 ppm steps on CLK0A/B enable real-time margin testing and dynamic frequency tuning without clock interruption
Sub-20 ps phase adjustment resolution	±45 ns range with 20 ps step size allows precise skew compensation between FPGA I/O banks or SerDes lanes
PCIe 2.0-compliant spread spectrum	Reduces EMI on 100 MHz outputs without violating PCIe jitter compliance limits (RMS ≤ 0.45 ps)

Applications

Ethernet Switch Timing	PCIe 3.0 Clock Distribution
Use Scenario: Synchronizing multiple 10 GbE PHYs and packet processors in a Layer 3 switch ASIC platform. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, phase-aligned clocks at 156.25 MHz (XAUI), 125 MHz (SGMII), 100 MHz (PCIe REFCLK), and 25 MHz (management interface). Use Value: 0.7 ps RMS jitter ensures <10⁻¹² BER under worst-case crosstalk; independent VDDO supplies eliminate noise coupling between high-speed and management domains.	Use Scenario: Delivering compliant reference clocks to CPU, GPU, and NVMe controllers sharing a single PCIe root complex. IC Role / Device Role / Timing Role: Generating four synchronized 100 MHz PCIe 3.0 REFCLK signals with SSC enabled on two outputs to meet FCC Class B emissions limits. Use Value: Spread spectrum on selected outputs reduces peak radiated emissions by >10 dB while maintaining 0.45 ps RMS jitter compliance per PCI-SIG specification.
FPGA & SoC Clocking	Broadcast Video Timing
Use Scenario: Providing clock sources for transceiver banks, memory interfaces, and logic fabric in Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Supplying 297 MHz (HDMI 2.1 TMDS), 148.5 MHz (SMPTE ST 2110), 100 MHz (AXI interconnect), and 27 MHz (video processing subsystem) from a single chip. Use Value: Any-frequency synthesis eliminates need for multiple crystals or discrete synthesizers; sub-20 ps phase steps align transceiver launch edges across banks.	Use Scenario: Master timing source for SDI routers, frame synchronizers, and IP video gateways requiring SMPTE 2081/2110 compliance. IC Role / Device Role / Timing Role: Generating 27 MHz (SDI), 74.25 MHz (3G-SDI), 148.5 MHz (12G-SDI), and 297 MHz (UHD-SDI) with <±500 fs period jitter stability over temperature. Use Value: 0 ppm frequency accuracy prevents frame slips in multi-device sync chains; LVDS outputs drive long backplane traces with <100 ps skew.

Ethernet Switch Timing

PCIe 3.0 Clock Distribution

Use Scenario: Synchronizing multiple 10 GbE PHYs and packet processors in a Layer 3 switch ASIC platform.

IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, phase-aligned clocks at 156.25 MHz (XAUI), 125 MHz (SGMII), 100 MHz (PCIe REFCLK), and 25 MHz (management interface).

Use Value: 0.7 ps RMS jitter ensures <10⁻¹² BER under worst-case crosstalk; independent VDDO supplies eliminate noise coupling between high-speed and management domains.

Use Scenario: Delivering compliant reference clocks to CPU, GPU, and NVMe controllers sharing a single PCIe root complex.

IC Role / Device Role / Timing Role: Generating four synchronized 100 MHz PCIe 3.0 REFCLK signals with SSC enabled on two outputs to meet FCC Class B emissions limits.

Use Value: Spread spectrum on selected outputs reduces peak radiated emissions by >10 dB while maintaining 0.45 ps RMS jitter compliance per PCI-SIG specification.

FPGA & SoC Clocking

Broadcast Video Timing

Use Scenario: Providing clock sources for transceiver banks, memory interfaces, and logic fabric in Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Supplying 297 MHz (HDMI 2.1 TMDS), 148.5 MHz (SMPTE ST 2110), 100 MHz (AXI interconnect), and 27 MHz (video processing subsystem) from a single chip.

Use Value: Any-frequency synthesis eliminates need for multiple crystals or discrete synthesizers; sub-20 ps phase steps align transceiver launch edges across banks.

Use Scenario: Master timing source for SDI routers, frame synchronizers, and IP video gateways requiring SMPTE 2081/2110 compliance.

IC Role / Device Role / Timing Role: Generating 27 MHz (SDI), 74.25 MHz (3G-SDI), 148.5 MHz (12G-SDI), and 297 MHz (UHD-SDI) with <±500 fs period jitter stability over temperature.

Use Value: 0 ppm frequency accuracy prevents frame slips in multi-device sync chains; LVDS outputs drive long backplane traces with <100 ps skew.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05192-GM	Higher integration: includes integrated crystal option, enhanced jitter performance (0.5 ps RMS), and I²C programmability	Preferred for new designs requiring field reconfiguration or tighter jitter budgets; not pin-compatible	Select when design requires post-production frequency updates or <0.6 ps RMS jitter for 400G Ethernet PHYs
ICS8430I-01T	Fixed-frequency quad LVDS generator (no any-frequency synthesis); 1.2 ps RMS jitter; 3.3 V only core and outputs	Suitable only for static clock trees where frequencies are known pre-BOM freeze	Choose only if cost sensitivity outweighs flexibility needs and all required frequencies are integer multiples of a common base

Compared with Si5332A-D05192-GM, SI5334C-B05192-GM offers lower cost and simpler pin-control configuration but lacks I²C reprogrammability; versus ICS8430I-01T, it provides full frequency agility and mixed-voltage operation at the expense of higher design validation effort.

Availability

SI5334C-B05192-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe 3.0 host systems, broadcast video infrastructure, and FPGA-based prototyping requiring stable component supply across multi-year production cycles.

Supply support for SI5334C-B05192-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5334 product line was engineered for high-density, low-jitter clock generation in bandwidth-constrained systems such as telecom line cards, data center switches, and broadcast equipment - emphasizing pin-configurability, multi-format output flexibility, and factory-programmed reliability.

FAQ

What is the maximum output frequency supported by SI5334C-B05192-GM?

The SI5334C-B05192-GM supports up to 710 MHz on LVPECL and LVDS outputs when configured with appropriate MultiSynth dividers (e.g., Fvco/4 or Fvco/6 modes). For general-purpose use across all signal formats, the guaranteed range is 0.16–350 MHz. Frequencies above 350 MHz require validation per Table 4 in the datasheet Rev. 1.3 and are limited to specific output formats and divider configurations. SI5334C-B05192-GM must be operated within its specified thermal limits (θJA = 37 °C/W) when delivering sustained 710 MHz outputs.

Does SI5334C-B05192-GM support spread spectrum clocking (SSC)?

Yes, SI5334C-B05192-GM supports PCIe 2.0-compliant spread spectrum on any output clock operating at exactly 100 MHz with Rn divider set to 1. The modulation rate is 30–33 kHz with ±0.5% frequency deviation, reducing electromagnetic interference without violating PCIe jitter requirements. SSC is disabled by default and activated via pin strapping or factory programming - it is not available on non-100 MHz outputs or when Rn ≠ 1. SI5334C-B05192-GM does not support variable-rate or user-defined SSC profiles.

Can SI5334C-B05192-GM generate four different output frequencies simultaneously?

Yes, SI5334C-B05192-GM is explicitly designed for independent, any-frequency synthesis on all four differential output pairs. Each output (CLK0A/B through CLK3A/B) can be configured to a unique frequency - for example, 156.25 MHz, 125 MHz, 100 MHz, and 27 MHz - with zero ppm error and sub-ps jitter. This capability is enabled by four separate MultiSynth dividers and is confirmed in the Functional Block Diagram and Section 2.4 of the datasheet Rev. 1.3. SI5334C-B05192-GM maintains full independence even when mixing output formats (e.g., LVDS + HCSL) and supply voltages.

What reference inputs does SI5334C-B05192-GM accept?

SI5334C-B05192-GM accepts four types of reference inputs: (1) 8–30 MHz fundamental-mode crystal connected to IN1/IN2; (2) single-ended CMOS clock (5–200 MHz) on IN3 or IN4; (3) SSTL or HSTL clock (5–350 MHz) on IN3/IN4; and (4) differential clock (5–710 MHz) on IN1/IN2, IN5/IN6, or IN4/IN5 pairs. All inputs are validated across –40 °C to +85 °C. SI5334C-B05192-GM does not support internal oscillator bypass or external VCO inputs beyond these defined interfaces.

Is SI5334C-B05192-GM pin-compatible with other Si5334 variants?

Yes, all Si5334 variants - including SI5334C-B05192-GM - share identical 24-QFN pinout, footprint, and thermal pad layout per Package Outline document section 6 of the datasheet Rev. 1.3. Pin functions (e.g., IN1, CLK0A, VDDO0) are fixed across the family. Differences between variants (e.g., Si5334D vs. Si5334G) relate solely to factory-programmed features like phase/frequency control capability and are not reflected in pin assignment or electrical interface. SI5334C-B05192-GM may be substituted for other Si5334 part numbers in existing PCB layouts without modification.

SI5334C-B05192-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334C-B05192-GM FAQ

1.How can I place an order for SI5334C-B05192-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334C-B05192-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334C-B05192-GM reliable?

The price and inventory of SI5334C-B05192-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B05192-GM is usually 5 days.

3.What payment methods are accepted for SI5334C-B05192-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B05192-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334C-B05192-GM?

SI5334C-B05192-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334C-B05192-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334C-B05192-GM?

For technical support, including SI5334C-B05192-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B05192-GM requirements.

6.How does Aetrix verify that SI5334C-B05192-GM is sourced from the original manufacturer or authorized distributors?

All SI5334C-B05192-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B05192-GM meets industry standards.

7.What is the process for return or replacement of SI5334C-B05192-GM?

All SI5334C-B05192-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B05192-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334C-B05192-GM part is unused and in its original packaging.

Return procedure for SI5334C-B05192-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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