Skyworks Solutions Inc. SI5334C-B05500-GM

Overview

SI5334C-B05500-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, supporting frequencies up to 710 MHz (LVPECL/LVDS), 350 MHz (SSTL/HSTL), 250 MHz (HCSL), and 200 MHz (CMOS). It features MultiSynth fractional-N synthesis, 0.7 ps RMS typical phase jitter, and factory-programmed configuration for immediate operation at power-up. It is deployed in PCIe 3.0 timing, FPGA clocking, and broadcast video systems.

For engineers reviewing the SI5334C-B05500-GM datasheet, SI5334C-B05500-GM pinout, SI5334C-B05500-GM application, or SI5334C-B05500-GM equivalent, key selection considerations include output format flexibility per channel (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent VDDO voltage selection (1.5/1.8/2.5/3.3 V), 1 ppm frequency increment/decrement capability on CLK0A/B, ±45 ns programmable phase offset, and loss-of-signal/loss-of-lock monitoring via LOSLOL pin.

Technical Context

The SI5334C-B05500-GM integrates a fully on-chip fractional-N PLL with VCO, loop filter, and multi-stage synthesis - including one primary PLL stage and four independent MultiSynth dividers - enabling zero-ppm frequency accuracy across all outputs. Its input stage accepts crystal (8–30 MHz) or differential/single-ended clocks (5–710 MHz), while each output driver supports independent signal format and supply voltage selection.

It implements pin-controlled real-time adjustments: frequency increment/decrement (1 ppm steps, glitchless, max 1.5 MHz update rate on CLK0A/B only) and phase increment/decrement (<20 ps step resolution, ±45 ns range, 0.16–350 MHz valid range). Spread spectrum is PCI Express 2.0 compliant and available only on 100 MHz outputs with Rn divider = 1.

Key Specifications

Pinout & Package

SI5334C-B05500-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5334 family layout and validated for this variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5332A-D05500-GM and ICS8430I-01T, SI5334C-B05500-GM uniquely delivers pin-controlled, any-frequency synthesis in a 4-output QFN without I²C overhead - ideal for PCIe 3.0 and broadcast video where deterministic startup and sub-ps jitter are non-negotiable.

Availability

SI5334C-B05500-GM is available at Aetrix Electronics and suitable for PCIe 3.0 timing, FPGA clocking, and broadcast video applications requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.

Supply support for SI5334C-B05500-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5334 product line delivers pin-configurable, low-jitter clock generators for high-speed digital systems where deterministic timing, multi-format output flexibility, and zero-ppm synthesis accuracy are essential - targeting networking, datacenter, and professional A/V infrastructure.

FAQ

What is the maximum supported output frequency for SI5334C-B05500-GM in LVPECL mode?

The SI5334C-B05500-GM supports up to 710 MHz on LVPECL outputs (CLK0A/B through CLK3A/B), verified per Skyworks datasheet Table 4. This enables direct clocking of 28 Gbps SerDes lanes and 10GBASE-KR PHYs without external frequency multiplication. Operation above 350 MHz requires Fvco/4 or Fvco/6 synthesis mode and is limited to two unique frequencies simultaneously.

Does SI5334C-B05500-GM support spread spectrum clocking (SSC)?

Yes, SI5334C-B05500-GM supports PCIe 2.0-compliant spread spectrum on any output clock operating at exactly 100 MHz with Rn divider set to 1. The modulation rate is 30–33 kHz with ±0.5% deviation, reducing EMI without violating PCIe jitter limits. SSC is not available on other frequencies or in non-HCSL formats per datasheet Section 2.10 and Table 6.

Can SI5334C-B05500-GM generate different output formats simultaneously?

Yes, SI5334C-B05500-GM supports mixed output formats: each of the four differential output pairs (CLK0A/B to CLK3A/B) can be independently configured for LVPECL, LVDS, HCSL, CML, SSTL, or HSTL. Format selection is factory-programmed and does not require runtime I²C commands - enabling simultaneous 100 MHz HCSL (PCIe), 125 MHz LVDS (GbE), and 27 MHz LVPECL (video) outputs.

What is the function of the LOSLOL pin on SI5334C-B05500-GM?

The LOSLOL pin on SI5334C-B05500-GM is an open-drain alarm output that asserts low within 5 µs of detecting either loss-of-signal (on any input clock) or loss-of-lock (PLL unlock). It deasserts within 100 ns to 1 µs after recovery. This pin provides hardware-level fault signaling to system supervisors or FPGAs without software intervention - critical for carrier-grade telecom and broadcast equipment uptime monitoring.

Is SI5334C-B05500-GM compatible with a 25 MHz crystal reference?

No, SI5334C-B05500-GM is not rated for 25 MHz crystal operation. Per Skyworks datasheet Tables 6–9, its crystal input supports only 8–30 MHz, with specific load capacitance and ESR requirements segmented by frequency band (e.g., 8–11 MHz, 11–19 MHz, etc.). A 25 MHz crystal falls within the 19–26 MHz band and is supported - but 25 MHz is explicitly listed as valid in Table 8 (19–26 MHz range), confirming compatibility when CL = 17–19 pF and rESR ≤ 100 Ω.