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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334C-B05500-GMR

Name: SI5334C-B05500-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5334C-B05500-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334C-B05500-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334C-B05500-GMR.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334C-B05500-GMR from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs, 0.7 ps RMS typical phase jitter, 350 MHz max integer-output frequency (up to 710 MHz at select frequencies), and factory-programmed configuration for immediate operation on power-up. It serves as a high-precision timing source in PCIe 3.0, Ethernet switch/router, and FPGA clocking systems.

For engineers reviewing the SI5334C-B05500-GMR datasheet, SI5334C-B05500-GMR pinout, SI5334C-B05500-GMR application, or SI5334C-B05500-GMR equivalent, key selection considerations include its MultiSynth-based fractional-N synthesis, independent output voltage per driver (1.5/1.8/2.5/3.3 V), zero ppm frequency accuracy, 4×4 mm 24-QFN package, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL signal formats.

Technical Context

The SI5334C-B05500-GMR integrates a fully on-chip fractional-N PLL with phase detector, charge pump, loop filter, VCO, and R/N/M dividers, enabling precise frequency synthesis across four independent MultiSynth output stages. Each output supports integer or fractional division with <1 ppb resolution and operates up to Fvco/8 (350 MHz) or select higher frequencies (710 MHz).

Its input stage accepts 8–30 MHz crystals or 5–710 MHz differential/single-ended reference clocks, while the output stage provides per-driver supply voltage control (VDDO0–VDDO3), programmable initial phase offset (±45 ns), and 20 ps phase step resolution. Loss-of-signal (LOSLOL) and optional zero-delay feedback mode further enhance system-level timing robustness.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B through CLK3A/B), each independently configurable
Max output frequency	350 MHz for integer synthesis; up to 710 MHz at select frequencies (e.g., 367–473.33 MHz, 550–710 MHz)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), verified for LVDS/HCSL/LVPECL outputs with low-noise differential input
Frequency accuracy	True 0 ppm error on all outputs due to MultiSynth fractional-N synthesis with no rounding error
Supply voltages	Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver (VDDO0–VDDO3)
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial applications

Pinout & Package

SI5334C-B05500-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5334 family and validated for this variant.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input (primary)	Accepts 5–710 MHz AC-coupled differential clock; internal 10 kΩ termination
IN3 / IN4	Single-ended reference input	Supports 5–200 MHz CMOS/SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
IN5 / IN6	Differential feedback input (FDBK/FDBKB)	Enables zero-delay mode when connected to CLKx output; supports 5–710 MHz
CLK0A / CLK0B through CLK3A / CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CML/SSTL/HSTL
VDDO0–VDDO3	Output buffer supply rails	Independent 1.5/1.8/2.5/3.3 V supplies per output pair - enables mixed-voltage system interfacing
VDD	Core supply	1.8/2.5/3.3 V core logic supply; IDD = 45 mA typical at 100 MHz on all outputs
LOSLOL	Loss-of-signal/loss-of-lock alarm	Open-drain output asserting within 5 µs of input loss or PLL unlock; VOL ≤ 0.4 V @ 3 mA
OEB	Output enable/disable	Active-low control; disables all outputs simultaneously without affecting internal PLL operation
RSVD_GND	Reserved ground	Must be connected to GND per layout guidelines; improves noise immunity and thermal performance

Key Features

Feature	Design Value
MultiSynth frequency synthesis	Enables any-frequency generation on all four outputs with zero ppm error and <1 ppb resolution
Independent output voltage per driver	Allows simultaneous interfacing to multiple voltage-domain devices (e.g., 1.8 V FPGA + 3.3 V PHY) without level shifters
Glitchless frequency increment/decrement	Adjusts CLK0A/B frequency in 1 ppm steps over full range (≤350 MHz), supporting margin testing and dynamic clock tuning
Programmable phase offset	±45 ns initial phase adjustment per output with 20 ps step resolution, enabling precise skew management in multi-clock domains
PCIe-compliant spread spectrum	SSC available on any 100 MHz output with –0.5% deviation at 30–33 kHz, reducing EMI without violating PCIe 2.0 spec

Applications

PCI Express 3.0 Clocking	Ethernet Switch/Routing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe 3.0 root ports and endpoints in a server motherboard. IC Role / Device Role / Timing Role: Primary clock generator delivering low-jitter, zero-ppm-accurate clocks compliant with PCIe 3.0 jitter limits (≤0.45 ps RMS). Use Value: Meets Intel Clock Jitter Tool requirements for PCIe 3.0 common clock architecture with 0.7 ps RMS typical jitter and deterministic jitter <10 ps pk-pk.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in a Layer 3 switch. IC Role / Device Role / Timing Role: Quad-output timing hub distributing phase-aligned clocks across multiple data-path ICs with sub-100 ps inter-output skew. Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter, satisfying IEEE 802.3ba jitter budgets for 10 GbE backplane interfaces.
FPGA & Processor Clocking	Broadcast Video Timing
Use Scenario: Supplying independent clocks to Xilinx Versal FPGA banks (100 MHz PL, 200 MHz PS, 300 MHz DDR, 150 MHz GTY transceivers). IC Role / Device Role / Timing Role: Configurable clock source enabling mixed-signal domain partitioning with per-bank voltage and format control. Use Value: Delivers LVDS (1.8 V), HCSL (2.5 V), and CMOS (3.3 V) outputs simultaneously from one 4×4 mm package, eliminating discrete clock trees.	Use Scenario: Generating SMPTE ST 2042/2082 compliant 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks for 4K/8K video encoders and frame synchronizers. IC Role / Device Role / Timing Role: Precision timing generator maintaining frame-locked synchronization across multiple video processing pipelines. Use Value: Provides <±1 ppm frequency accuracy and <20 ps phase step resolution for genlock and lip-sync alignment in broadcast infrastructure.

PCI Express 3.0 Clocking

Ethernet Switch/Routing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe 3.0 root ports and endpoints in a server motherboard.

IC Role / Device Role / Timing Role: Primary clock generator delivering low-jitter, zero-ppm-accurate clocks compliant with PCIe 3.0 jitter limits (≤0.45 ps RMS).

Use Value: Meets Intel Clock Jitter Tool requirements for PCIe 3.0 common clock architecture with 0.7 ps RMS typical jitter and deterministic jitter <10 ps pk-pk.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in a Layer 3 switch.

IC Role / Device Role / Timing Role: Quad-output timing hub distributing phase-aligned clocks across multiple data-path ICs with sub-100 ps inter-output skew.

Use Value: Achieves <100 ps output-to-output skew and 0.7 ps RMS jitter, satisfying IEEE 802.3ba jitter budgets for 10 GbE backplane interfaces.

FPGA & Processor Clocking

Broadcast Video Timing

Use Scenario: Supplying independent clocks to Xilinx Versal FPGA banks (100 MHz PL, 200 MHz PS, 300 MHz DDR, 150 MHz GTY transceivers).

IC Role / Device Role / Timing Role: Configurable clock source enabling mixed-signal domain partitioning with per-bank voltage and format control.

Use Value: Delivers LVDS (1.8 V), HCSL (2.5 V), and CMOS (3.3 V) outputs simultaneously from one 4×4 mm package, eliminating discrete clock trees.

Use Scenario: Generating SMPTE ST 2042/2082 compliant 74.25 MHz, 148.5 MHz, and 297 MHz pixel clocks for 4K/8K video encoders and frame synchronizers.

IC Role / Device Role / Timing Role: Precision timing generator maintaining frame-locked synchronization across multiple video processing pipelines.

Use Value: Provides <±1 ppm frequency accuracy and <20 ps phase step resolution for genlock and lip-sync alignment in broadcast infrastructure.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05500-GM	Higher integration: 8 outputs, integrated EEPROM, I²C programmability; larger 32-QFN (5×5 mm); 0.5 ps RMS jitter	Required for designs needing field reconfiguration or >4 outputs; not pin-compatible	Select when flexibility beyond factory programming is needed; SI5334C-B05500-GMR remains optimal for cost-sensitive, fixed-configuration quad-clock use cases.
ICS8430I-01T	Lower performance: 1.2 ps RMS jitter, 250 MHz max output, no fractional synthesis; 32-TQFP package; no per-output voltage control	Suitable only for legacy 2.5 GbE or non-PCIe applications where jitter margin is relaxed	Choose only if footprint compatibility with existing TQFP layouts is mandatory and jitter specs permit ≥1.2 ps RMS.

Compared with Si5332A-D05500-GM and ICS8430I-01T, SI5334C-B05500-GMR delivers superior jitter (0.7 ps vs. 0.5/1.2 ps), true any-frequency synthesis with zero ppm error, and compact 24-QFN packaging - making it the optimal choice for PCIe 3.0, 10 GbE, and FPGA clocking where precision, density, and fixed-configuration reliability are prioritized.

Availability

SI5334C-B05500-GMR is available at Aetrix Electronics and suitable for PCIe 3.0 reference clocking, Ethernet switch/router timing, and FPGA/processor clock distribution requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for SI5334C-B05500-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for communications, automotive, and industrial markets.

The Si5334 product line was designed to deliver ultra-low-jitter, any-frequency clock generation in space-constrained applications - targeting high-speed serial interface timing (PCIe, Ethernet, Fibre Channel) where traditional crystal oscillators or fixed-ratio PLLs fall short.

FAQ

What is the maximum output frequency supported by the SI5334C-B05500-GMR?

The SI5334C-B05500-GMR supports up to 350 MHz for general integer-mode synthesis across all outputs. At select frequencies - specifically 367–473.33 MHz and 550–710 MHz - it also delivers valid outputs, enabled by its MultiSynth architecture operating above Fvco/8. These higher frequencies are validated per Skyworks' standard frequency plans and require appropriate VCO calibration.

Does the SI5334C-B05500-GMR support spread spectrum clocking (SSC)?

Yes, the SI5334C-B05500-GMR supports PCIe 2.0-compliant spread spectrum on any output clock running at exactly 100 MHz, with –0.5% frequency deviation modulated at 30–33 kHz. This feature is enabled via factory programming and requires the Rn divider to be set to 1 on the target output - no external components or runtime control are needed.

Can the SI5334C-B05500-GMR generate different output formats simultaneously?

Yes, the SI5334C-B05500-GMR supports concurrent LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL outputs - one format per differential pair (CLK0A/B through CLK3A/B). Each output driver has its own VDDO supply rail (1.5/1.8/2.5/3.3 V), allowing direct interfacing to mixed-voltage systems without external level shifters or translators.

What is the purpose of the LOSLOL pin on the SI5334C-B05500-GMR?

The LOSLOL pin on the SI5334C-B05500-GMR is an open-drain alarm output that asserts low within 5 µs of detecting either loss-of-signal on the primary reference input (IN1/IN2) or loss-of-lock in the PLL. It deasserts within 100 ns–1 µs after recovery, providing real-time fault monitoring for system-level watchdog or fail-safe logic without requiring host processor intervention.

Is the SI5334C-B05500-GMR pin-compatible with other Si5334 variants?

Yes, all Si5334 variants - including SI5334C-B05500-GMR - share identical 24-QFN pinout, electrical characteristics, and functional block diagram. Differences lie solely in factory-programmed configuration (frequency plan, output format, voltage, phase offset), meaning PCB layout and schematic symbols are fully reusable across the Si5334 family.

SI5334C-B05500-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334C-B05500-GMR FAQ

1.How can I place an order for SI5334C-B05500-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334C-B05500-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334C-B05500-GMR reliable?

The price and inventory of SI5334C-B05500-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B05500-GMR is usually 5 days.

3.What payment methods are accepted for SI5334C-B05500-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B05500-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334C-B05500-GMR?

SI5334C-B05500-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334C-B05500-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334C-B05500-GMR?

For technical support, including SI5334C-B05500-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B05500-GMR requirements.

6.How does Aetrix verify that SI5334C-B05500-GMR is sourced from the original manufacturer or authorized distributors?

All SI5334C-B05500-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B05500-GMR meets industry standards.

7.What is the process for return or replacement of SI5334C-B05500-GMR?

All SI5334C-B05500-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B05500-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334C-B05500-GMR part is unused and in its original packaging.

Return procedure for SI5334C-B05500-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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