Skyworks Solutions Inc. SI5334C-B05752-GM

Overview

SI5334C-B05752-GM from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz using MultiSynth fractional-N synthesis, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, and operates from 1.8/2.5/3.3 V core and per-output supply voltages - deployed in PCIe 3.0 timing, FPGA clocking, and broadcast video systems.

For engineers reviewing the SI5334C-B05752-GM datasheet, SI5334C-B05752-GM pinout, SI5334C-B05752-GM application, or SI5334C-B05752-GM equivalent, this page provides verified technical context, factory-programmed configuration details, jitter performance data at 125 MHz and 155.52 MHz, pin-level control logic for phase/frequency adjustment, and validated alternative options for multi-protocol clocking designs.

Technical Context

The SI5334C-B05752-GM implements a two-stage synthesis architecture: a primary fractional-N PLL (phase detector, charge pump, loop filter, VCO) generating a high-frequency VCO signal up to ~4.2 GHz, followed by four independent MultiSynth dividers enabling zero-ppm frequency synthesis on each of CLK0A/B through CLK3A/B. Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each output driver supports independent voltage selection (1.5/1.8/2.5/3.3 V), format selection (LVPECL up to 710 MHz, LVDS up to 350 MHz, HCSL up to 250 MHz, CMOS up to 200 MHz), and features pin-controlled phase adjustment (±45 ns range, <20 ps step) and frequency increment/decrement (1 ppm steps, glitchless, on CLK0A/B only). Loss-of-signal (LOSLOL) and optional zero-delay feedback mode are supported.

Key Specifications

Pinout & Package

SI5334C-B05752-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad (RoHS-compliant, moisture sensitivity level 3). Pin assignments follow Skyworks' standard Si5334 pinout: dual differential inputs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/B–CLK3A/B), dedicated LOSLOL alarm output, OEB (output enable bar), and separate VDD, VDDO0–VDDO3, and GND pins.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Compared with Si5332A-D05752-GM and ICS853S01AGI-01LFT, SI5334C-B05752-GM uniquely balances factory-programmed simplicity, 710 MHz capability, and pin-level phase/frequency control - making it optimal for PCIe 3.0, broadcast video, and FPGA platforms requiring guaranteed jitter performance without software overhead.

Availability

SI5334C-B05752-GM is available at Aetrix Electronics and suitable for PCIe 3.0 timing, broadcast video synchronization, and FPGA clock distribution requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for SI5334C-B05752-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog solutions for infrastructure, automotive, and industrial markets.

The Si5334 family was designed for high-reliability, multi-protocol clock generation in systems demanding sub-1 ps jitter, flexible output formatting, and factory-programmed simplicity - targeting telecom line cards, enterprise networking, and broadcast equipment.

FAQ

What is the factory-programmed configuration of SI5334C-B05752-GM?

The SI5334C-B05752-GM is pre-programmed with a specific frequency plan and output configuration stored in on-chip OTP memory. Upon power-up, it begins operation immediately without I²C initialization - delivering four predefined differential clock outputs derived from an internal crystal oscillator or external reference. Configuration details (frequencies, formats, voltages) are fixed and documented in Skyworks' standard frequency plan B05752.

Does SI5334C-B05752-GM support spread spectrum clocking (SSC)?

Yes, SI5334C-B05752-GM supports PCIe 2.0-compliant spread spectrum on any output clock operating at exactly 100 MHz with its Rn divider set to 1. The modulation is ±0.5% deviation at 30–33 kHz, implemented entirely in hardware without external components or software control - reducing EMI in dense board layouts while maintaining timing integrity.

Can SI5334C-B05752-GM generate 156.25 MHz and 148.3517 MHz simultaneously?

Yes, SI5334C-B05752-GM can generate both 156.25 MHz and 148.3517 MHz simultaneously on separate outputs. Its MultiSynth architecture supports independent fractional synthesis per channel, enabling precise, zero-ppm generation of these IEEE 802.3 and SMPTE ST 292/372 rates from a common 25 MHz or 19.44 MHz reference - with measured jitter of ≤0.7 ps RMS at both frequencies.

What is the maximum output frequency supported by SI5334C-B05752-GM in LVDS mode?

The maximum output frequency for SI5334C-B05752-GM in LVDS mode is 350 MHz, as specified in Table 4 of the datasheet. This applies to both LVDS 2.5 V and 3.3 V configurations. At 350 MHz, the device maintains 45–55% duty cycle and ≤450 ps rise/fall time, meeting JEDEC JESD79-4 DDR4 timing requirements for high-speed memory interfaces.

How does the LOSLOL pin function on SI5334C-B05752-GM?

The LOSLOL pin on SI5334C-B05752-GM is an open-drain, active-low alarm output that asserts within 2.6–5 µs of input clock loss or PLL unlock. It monitors both reference input integrity (via IN1/IN2 or IN3/IN4) and internal lock status, providing hardware-level fault detection for system watchdogs or FPGA-based health monitoring - without requiring I²C polling or external comparators.