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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334C-B05946-GM

Name: SI5334C-B05946-GM
Brand: Skyworks Solutions Inc.
SKU: SI5334C-B05946-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334C-B05946-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334C-B05946-GM.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334C-B05946-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, supporting frequencies up to 350 MHz (and select outputs to 710 MHz), 0.7 ps RMS typical phase jitter, and zero ppm frequency error via MultiSynth synthesis. It operates from 1.8/2.5/3.3 V core supply and targets PCIe 2.0/3.0, Ethernet switch/router, and FPGA clocking applications.

For engineers reviewing the SI5334C-B05946-GM datasheet, SI5334C-B05946-GM pinout, SI5334C-B05946-GM application, or SI5334C-B05946-GM equivalent, key selection criteria include independent output format support (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), per-output voltage control (1.5–3.3 V), glitchless 1 ppm frequency increment/decrement on CLK0A/B, and loss-of-lock/loss-of-signal alarm capability.

Technical Context

The SI5334C-B05946-GM integrates a fractional-N PLL with on-chip VCO and four independent MultiSynth dividers, enabling integer or fractional frequency synthesis per output with <20 ps phase step resolution and ±45 ns programmable initial phase offset. Input flexibility includes 8–30 MHz crystal or 5–710 MHz differential/single-ended reference clocks.

Its output stage supports mixed-signal operation: each of the four differential outputs (CLK0A/B through CLK3A/B) has dedicated VDDOx supply (1.4–3.63 V), enabling simultaneous LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL signaling at different voltages and frequencies - all without I²C configuration.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B); supports 8 single-ended or mixed-mode operation
Frequency range	0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS on select outputs
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), verified for 125 MHz GbE and 155.52 MHz OC-12 applications
Core supply	1.8 V / 2.5 V / 3.3 V ±10%; 45 mA typical current at 100 MHz on all outputs with 25 MHz refclk
Operating temperature	–40 °C to +85 °C ambient, qualified for industrial and telecom line card environments
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad
Input reference	Crystal (8–30 MHz) or AC/DC-coupled clock (5–710 MHz differential; 5–350 MHz single-ended)

Pinout & Package

SI5334C-B05946-GM is housed in a 24-pin, 4 mm × 4 mm QFN package with exposed thermal pad (pin 1 marked by dot). Pin functions are defined per Skyworks Rev. 1.3 datasheet, with dedicated input, output, supply, and control terminals.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential clock inputs	Accept 5–710 MHz AC-coupled differential reference; require external 100 Ω termination
IN3/IN4	Single-ended clock inputs	Support 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B through CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL with dedicated VDDOx
VDDO0–VDDO3	Output buffer supplies	Independent 1.4–3.63 V supplies per output pair; enable mixed-voltage signaling
VDD	Core supply	1.8/2.5/3.3 V ±10% supply for PLL, logic, and MultiSynth blocks
LOSLOL	Loss-of-signal/loss-of-lock alarm	Open-drain active-low output; asserts within 5 µs of input failure or PLL unlock
OEB	Output enable/disable	Active-low control; disables all outputs simultaneously with minimal propagation delay
RSVD_GND	Reserved ground	Internally connected to substrate; must be tied to PCB ground plane

Key Features

Feature	Design Value
MultiSynth frequency synthesis	Zero ppm error across full 0.16–350 MHz range; supports fractional-N division for arbitrary frequencies
Per-output signal format control	Each of four outputs independently selectable as LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL
Glitchless frequency tuning	1 ppm step size on CLK0A/B only; update rate up to 1.5 MHz; no output interruption during adjustment
Programmable phase offset	±45 ns range with <20 ps resolution per output; enables precise inter-clock timing alignment
PCIe-compliant spread spectrum	Available on any 100 MHz output with Rn divider = 1; ±0.5% deviation at 30–33 kHz modulation rate
Zero-delay mode support	Optional external feedback path via FDBK/FDBKB pins; eliminates static phase offset between ref and output

Applications

Ethernet Switch/Router Timing	PCI Express 2.0/3.0 Clocking
Use Scenario: Synchronizing multi-lane 1/10 GbE PHYs, MACs, and packet processors in enterprise and data center switches. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz clocks with sub-ps jitter for SerDes lane alignment. Use Value: Meets IEEE 802.3 clause 49 jitter limits (0.7 ps RMS) and enables deterministic latency across switching fabric.	Use Scenario: Delivering compliant reference clocks to PCIe root complex, endpoint, and switch ICs in servers and storage controllers. IC Role / Device Role / Timing Role: Generating 100 MHz HCSL clocks with PCIe 2.1/3.0 common-clock jitter compliance (≤0.45 ps RMS). Use Value: Eliminates need for multiple discrete oscillators; supports spread spectrum on 100 MHz outputs to reduce EMI.
FPGA and Processor Clocking	Broadcast Video/Audio Timing
Use Scenario: Supplying multiple synchronized clocks to heterogeneous SoCs, FPGAs, DDR memory interfaces, and ADC/DAC subsystems. IC Role / Device Role / Timing Role: Providing independent 100 MHz system clock, 200 MHz DDR interface clock, and 48 MHz peripheral clock from single device. Use Value: Reduces BOM count and layout complexity while maintaining <10 ps cycle-cycle jitter for timing-critical logic paths.	Use Scenario: Generating SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with ultra-low jitter for broadcast encoders/decoders. IC Role / Device Role / Timing Role: Acting as master timing source for genlock, frame sync, and pixel clock distribution in SDI and IP video systems. Use Value: Achieves –126 dBc/Hz phase noise at 10 kHz offset, meeting ITU-R BT.601 spectral purity requirements.

Ethernet Switch/Router Timing

PCI Express 2.0/3.0 Clocking

Use Scenario: Synchronizing multi-lane 1/10 GbE PHYs, MACs, and packet processors in enterprise and data center switches.

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz clocks with sub-ps jitter for SerDes lane alignment.

Use Value: Meets IEEE 802.3 clause 49 jitter limits (0.7 ps RMS) and enables deterministic latency across switching fabric.

Use Scenario: Delivering compliant reference clocks to PCIe root complex, endpoint, and switch ICs in servers and storage controllers.

IC Role / Device Role / Timing Role: Generating 100 MHz HCSL clocks with PCIe 2.1/3.0 common-clock jitter compliance (≤0.45 ps RMS).

Use Value: Eliminates need for multiple discrete oscillators; supports spread spectrum on 100 MHz outputs to reduce EMI.

FPGA and Processor Clocking

Broadcast Video/Audio Timing

Use Scenario: Supplying multiple synchronized clocks to heterogeneous SoCs, FPGAs, DDR memory interfaces, and ADC/DAC subsystems.

IC Role / Device Role / Timing Role: Providing independent 100 MHz system clock, 200 MHz DDR interface clock, and 48 MHz peripheral clock from single device.

Use Value: Reduces BOM count and layout complexity while maintaining <10 ps cycle-cycle jitter for timing-critical logic paths.

Use Scenario: Generating SMPTE ST 2059-2–compliant 27 MHz, 74.25 MHz, and 148.5 MHz video clocks with ultra-low jitter for broadcast encoders/decoders.

IC Role / Device Role / Timing Role: Acting as master timing source for genlock, frame sync, and pixel clock distribution in SDI and IP video systems.

Use Value: Achieves –126 dBc/Hz phase noise at 10 kHz offset, meeting ITU-R BT.601 spectral purity requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05946-GM	Higher integration: 8 outputs, integrated EEPROM, I²C programmability; 0.5 ps RMS jitter; supports JESD204B deterministic latency	Required for multi-device synchronization, JESD204B subclass 1, or field-reprogrammable configurations	Select when design requires >4 outputs, dynamic reconfiguration, or deterministic phase alignment across boards
ICS8430I-01T	Fixed-frequency quad LVDS generator; no frequency synthesis; 1.2 ps RMS jitter; 3.3 V only; no spread spectrum or phase control	Limited to static clock trees where all frequencies are known pre-production	Choose for cost-sensitive, low-jitter applications with fixed 100/125/156.25 MHz outputs and no tuning needs

Compared with Si5332A-D05946-GM, SI5334C-B05946-GM offers simpler pin-control operation and lower power but lacks I²C configurability and JESD204B support; versus ICS8430I-01T, it delivers full any-frequency synthesis and per-output flexibility at higher complexity and cost.

Availability

SI5334C-B05946-GM is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe 2.0/3.0 host controller, and FPGA clocking applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5334C-B05946-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5334 product line delivers high-performance, pin-configurable clock generators optimized for multi-protocol timing in networking, computing, and broadcast infrastructure - emphasizing low jitter, flexible output formatting, and zero-configuration startup.

FAQ

What is the maximum output frequency supported by SI5334C-B05946-GM?

SI5334C-B05946-GM supports up to 350 MHz on all output formats (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL) and select frequencies up to 710 MHz for LVPECL and LVDS outputs. The actual achievable frequency depends on the selected output format and VDDO supply voltage, with 710 MHz limited to LVPECL/LVDS at 3.3 V VDDO and proper load termination.

Does SI5334C-B05946-GM require I²C programming to operate?

No, SI5334C-B05946-GM does not require I²C programming. It is factory-programmed with a predefined configuration stored in one-time-programmable (OTP) memory and begins operation immediately upon power-up using pin-strapped settings. All frequency, format, and voltage configurations are set at manufacture and controlled via hardware pins.

Can SI5334C-B05946-GM generate spread spectrum clocking for EMI reduction?

Yes, SI5334C-B05946-GM supports PCIe 2.0–compliant spread spectrum on any output clock operating at exactly 100 MHz with its Rn divider set to 1. The modulation is ±0.5% deviation at 30–33 kHz, and it can be enabled independently per output without affecting other channels.

What input reference options are supported by SI5334C-B05946-GM?

SI5334C-B05946-GM accepts an 8–30 MHz fundamental-mode crystal directly, or external clock inputs including: differential (5–710 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), and single-ended (5–200 MHz). Input slew rates must exceed 0.3 V/ns (differential) or 1.0 V/ns (single-ended) for optimal jitter performance.

How is phase alignment managed across the four outputs of SI5334C-B05946-GM?

SI5334C-B05946-GM provides independent programmable initial phase offset (±45 ns range) and real-time phase increment/decrement (20 ps steps) on each output. These adjustments are pin-controlled and do not require I²C communication, enabling deterministic inter-output skew control for timing-critical applications like SerDes lane deskew.

SI5334C-B05946-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334C-B05946-GM FAQ

1.How can I place an order for SI5334C-B05946-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334C-B05946-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334C-B05946-GM reliable?

The price and inventory of SI5334C-B05946-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B05946-GM is usually 5 days.

3.What payment methods are accepted for SI5334C-B05946-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B05946-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334C-B05946-GM?

SI5334C-B05946-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334C-B05946-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334C-B05946-GM?

For technical support, including SI5334C-B05946-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B05946-GM requirements.

6.How does Aetrix verify that SI5334C-B05946-GM is sourced from the original manufacturer or authorized distributors?

All SI5334C-B05946-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B05946-GM meets industry standards.

7.What is the process for return or replacement of SI5334C-B05946-GM?

All SI5334C-B05946-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B05946-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334C-B05946-GM part is unused and in its original packaging.

Return procedure for SI5334C-B05946-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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