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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334C-B05946-GMR

Name: SI5334C-B05946-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5334C-B05946-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334C-B05946-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334C-B05946-GMR.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334C-B05946-GMR from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz using MultiSynth fractional-N synthesis, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, and operates from 1.8/2.5/3.3 V core and per-output supply voltages - deployed in PCIe 3.0 timing, FPGA clocking, and broadcast video systems.

For engineers reviewing the SI5334C-B05946-GMR datasheet, SI5334C-B05946-GMR pinout, SI5334C-B05946-GMR application, or SI5334C-B05946-GMR equivalent, key selection criteria include its 4× independent differential outputs, factory-programmed configuration, zero-ppm frequency accuracy, 24-pin 4×4 mm QFN package, and support for glitchless 1 ppm frequency increment/decrement on CLK0A/B.

Technical Context

The SI5334C-B05946-GMR integrates a fully on-chip fractional-N PLL (phase detector, charge pump, loop filter, VCO, and R/N dividers) plus four independent MultiSynth output synthesis stages. Each MultiSynth supports integer or fractional division to generate any output frequency up to 350 MHz (or select frequencies to 710 MHz), with programmable initial phase offset (±45 ns) and <20 ps phase step resolution.

Input flexibility includes crystal (8–30 MHz), single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. Output drivers are individually voltage-configurable (1.5/1.8/2.5/3.3 V) and format-selectable, enabling mixed-signal system interfacing without level-shifting components.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B through CLK3A/B), each independently configurable
Frequency range	0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS with specific constraints
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), enabling compliance with PCIe 3.0 and 10GbE jitter budgets
Core supply voltage	1.8 V, 2.5 V, or 3.3 V - selectable per design; supports mixed-voltage system integration
Output supply per channel	VDDO0–VDDO3 independently set to 1.5/1.8/2.5/3.3 V - enables direct interface to diverse logic families
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch - space-constrained PCBs with thermal resistance θJA = 37 °C/W
Operating temperature	–40 °C to +85 °C - qualified for industrial and telecom line card environments

Pinout & Package

SI5334C-B05946-GMR is housed in a 24-lead, 4 mm × 4 mm, 0.5 mm pitch QFN package with exposed thermal pad. Pin assignments follow the standard Si5334 top-view layout.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential output pair 0	Primary output channel supporting LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL; frequency and phase independently adjustable
CLK1A / CLK1B	Differential output pair 1	Second independent output; supports same format/voltage flexibility as CLK0; no frequency increment/decrement control
CLK2A / CLK2B	Differential output pair 2	Third independent output; identical configurability to CLK1; used for multi-clock domain synchronization
CLK3A / CLK3B	Differential output pair 3	Fourth independent output; supports full format and voltage selection; enables quad-domain timing distribution
IN1 / IN2	Differential reference input	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination; slew rate >0.3 V/ns recommended for low jitter
IN3 / IN4	Single-ended reference input	Supports 5–200 MHz CMOS-level clock; VIH ≥ 0.7×VDD, VIL ≤ 0.3×VDD; 20 kΩ internal pull-up/pull-down options
IN5 / IN6	Secondary differential reference input	Redundant or alternate differential reference path; identical specs to IN1/IN2; enables failover clocking
IN7	Crystal input (XTAL)	Connects to 8–30 MHz fundamental-mode crystal; on-chip load capacitance 11–13 pF; supports oscillator mode
VDD	Core supply	1.8/2.5/3.3 V supply for PLL, MultiSynth, and control logic; bypass capacitor required at pin
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output pair - enables mixed-voltage signaling without external regulators
OEB	Output enable (active-low)	Global enable/disable of all four differential output pairs; synchronous assertion/deassertion prevents glitches
LOSLOL	Loss-of-signal/loss-of-lock alarm	Open-drain output asserting low on input clock loss or PLL unlock; 3 mA sink capability; pull-up required
RSVD_GND	Reserved ground	No-connect pin; must be tied to GND per layout guidelines to maintain signal integrity and thermal performance
GND	Ground	Primary analog/digital return; connects to exposed thermal pad; requires solid plane under package

Key Features

Feature	Design Value
MultiSynth fractional-N synthesis	Enables any-frequency generation per output with zero ppm error and 0.7 ps RMS jitter - eliminates need for multiple fixed-frequency oscillators
Independent output voltage per driver	Each of four output pairs powered by dedicated VDDOx rail (1.5/1.8/2.5/3.3 V) - directly interfaces LVDS, HCSL, and CMOS loads without level shifters
Glitchless 1 ppm frequency increment/decrement	Available on CLK0A/B only; enables real-time margin testing and dynamic frequency tuning without cycle slips or phase discontinuities
Programmable ±45 ns phase offset with 20 ps steps	Per-output phase alignment critical for SerDes deskew, DDR timing closure, and multi-lane synchronization
PCIe 2.0-compliant spread spectrum	Configurable on any 100 MHz output; reduces EMI peak emissions by modulating clock edge timing within regulatory limits
Zero-delay feedback mode	Uses FDBK/FDBKB pins to route one output back into PLL feedback path - eliminates static phase offset between reference and output clocks

Applications

PCI Express 3.0 Timing	FPGA and ASIC Clock Distribution
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe 3.0 root complex and endpoint devices in a server motherboard. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks - two for root complex, two for endpoints - with independent voltage control matching receiver I/O standards. Use Value: Meets PCIe 3.0 total jitter limit (<3.1 ps RMS) across all lanes while eliminating inter-lane skew via programmable phase offset.	Use Scenario: Driving high-speed transceivers, memory interfaces, and logic fabric in Xilinx Versal or Intel Agilex FPGAs requiring multiple independent clock domains. IC Role / Device Role / Timing Role: Configurable clock source generating 156.25 MHz GTY reference, 300 MHz DDR4 PHY clock, 100 MHz system management clock, and 250 MHz test clock - each with tailored output format and voltage. Use Value: Replaces three discrete oscillators and level shifters; reduces BOM count and layout area while enabling dynamic reconfiguration via pin control.
Broadcast Video Timing	Telecom Line Cards
Use Scenario: Generating SMPTE ST 2082 (12G-SDI) pixel clock (594 MHz), reference sync (27 MHz), audio sample clock (48 kHz), and genlock timing in professional video switchers. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer producing non-integer-related frequencies across four outputs - including ultra-low-jitter 594 MHz LVPECL for serial digital interface. Use Value: Achieves <0.7 ps RMS jitter at 594 MHz, satisfying SMPTE ST 2082 BER requirements; eliminates need for custom crystal oscillators per function.	Use Scenario: Supplying 155.52 MHz SONET OC-3/12, 622.08 MHz OC-48, 125 MHz Ethernet, and 10 MHz system reference in carrier-grade optical line cards. IC Role / Device Role / Timing Role: High-stability clock generator accepting 19.44 MHz crystal reference and synthesizing telecom-standard frequencies with zero ppm error and OC-12 compliant jitter (<1 ps RMS). Use Value: Passes ITU-T G.823/G.824 wander and jitter masks; supports holdover operation during reference loss via integrated LOSLOL alarm and fast PLL reacquisition (25 ms).

PCI Express 3.0 Timing

FPGA and ASIC Clock Distribution

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe 3.0 root complex and endpoint devices in a server motherboard.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four low-jitter, phase-aligned clocks - two for root complex, two for endpoints - with independent voltage control matching receiver I/O standards.

Use Value: Meets PCIe 3.0 total jitter limit (<3.1 ps RMS) across all lanes while eliminating inter-lane skew via programmable phase offset.

Use Scenario: Driving high-speed transceivers, memory interfaces, and logic fabric in Xilinx Versal or Intel Agilex FPGAs requiring multiple independent clock domains.

IC Role / Device Role / Timing Role: Configurable clock source generating 156.25 MHz GTY reference, 300 MHz DDR4 PHY clock, 100 MHz system management clock, and 250 MHz test clock - each with tailored output format and voltage.

Use Value: Replaces three discrete oscillators and level shifters; reduces BOM count and layout area while enabling dynamic reconfiguration via pin control.

Broadcast Video Timing

Telecom Line Cards

Use Scenario: Generating SMPTE ST 2082 (12G-SDI) pixel clock (594 MHz), reference sync (27 MHz), audio sample clock (48 kHz), and genlock timing in professional video switchers.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer producing non-integer-related frequencies across four outputs - including ultra-low-jitter 594 MHz LVPECL for serial digital interface.

Use Value: Achieves <0.7 ps RMS jitter at 594 MHz, satisfying SMPTE ST 2082 BER requirements; eliminates need for custom crystal oscillators per function.

Use Scenario: Supplying 155.52 MHz SONET OC-3/12, 622.08 MHz OC-48, 125 MHz Ethernet, and 10 MHz system reference in carrier-grade optical line cards.

IC Role / Device Role / Timing Role: High-stability clock generator accepting 19.44 MHz crystal reference and synthesizing telecom-standard frequencies with zero ppm error and OC-12 compliant jitter (<1 ps RMS).

Use Value: Passes ITU-T G.823/G.824 wander and jitter masks; supports holdover operation during reference loss via integrated LOSLOL alarm and fast PLL reacquisition (25 ms).

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05946-GM	Higher integration: 8 outputs, integrated EEPROM, I²C programmability; lower jitter (0.5 ps RMS); larger 32-QFN package	Required for designs needing field reconfiguration, more than 4 outputs, or tighter jitter budgets (e.g., 400G Ethernet)	Select when firmware-based frequency agility or >4 outputs are needed; not pin-compatible - requires PCB redesign
ICS8430I-01T	Fixed-frequency quad LVDS generator (100/125/156.25/200 MHz); no frequency synthesis; 1.2 ps RMS jitter; 3.3 V only; 24-TSSOP	Suitable only for static, known-frequency applications like basic Ethernet switches without margining or multi-standard support	Choose for cost-sensitive, non-reconfigurable designs where frequency flexibility is unnecessary and TSSOP packaging is acceptable

Compared with Si5332A-D05946-GM, SI5334C-B05946-GMR offers simpler pin-control setup and smaller footprint but lacks I²C reprogramming; versus ICS8430I-01T, it provides full any-frequency synthesis and voltage flexibility at the cost of higher complexity and price.

Availability

SI5334C-B05946-GMR is available at Aetrix Electronics and suitable for PCIe 3.0 timing, FPGA clocking, broadcast video systems, and telecom line cards requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.

Supply support for SI5334C-B05946-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for infrastructure, automotive, and mobile markets.

The Si5334 product line delivers highly flexible, low-jitter clock generation for systems demanding precise multi-frequency timing - designed specifically for high-speed serial interfaces, programmable logic, and broadcast equipment where frequency agility and phase control are critical.

FAQ

What is the maximum output frequency supported by SI5334C-B05946-GMR?

The SI5334C-B05946-GMR supports up to 710 MHz on LVPECL and LVDS outputs under specific conditions (e.g., Fvco/4 or Fvco/6 modes), while maintaining full functionality up to 350 MHz across all supported formats (LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL). Frequencies above 350 MHz require careful validation per Table 4 and Section 2.4 of the datasheet.

Does SI5334C-B05946-GMR support spread spectrum clocking (SSC)?

Yes, SI5334C-B05946-GMR supports PCIe 2.0-compliant spread spectrum on any output clock operating at exactly 100 MHz with Rn divider set to 1. The modulation rate is 30–33 kHz with ±0.5% frequency deviation - effective for reducing EMI peaks in dense PCB layouts without violating PCIe timing margins.

Can SI5334C-B05946-GMR generate different output formats simultaneously?

Yes, SI5334C-B05946-GMR allows independent configuration of each of its four differential output pairs (CLK0A/B through CLK3A/B) for different signal formats - e.g., CLK0A/B as LVDS, CLK1A/B as HCSL, CLK2A/B as LVPECL, and CLK3A/B as CMOS - with corresponding VDDOx supplies set accordingly.

What is the function of the LOSLOL pin on SI5334C-B05946-GMR?

The LOSLOL pin on SI5334C-B05946-GMR is an open-drain alarm output that asserts low when either input clock loss (tLOS = 2.6–5 µs) or PLL loss-of-lock (tLOL = 5–10 ms) is detected. It requires an external pull-up resistor and is used for system-level fault monitoring and failover triggering in telecom and industrial applications.

Is SI5334C-B05946-GMR pin-compatible with other Si5334 variants?

Yes, all Si5334 variants - including SI5334C-B05946-GMR - share the identical 24-pin QFN package, pinout, and electrical interface. Differences reside solely in factory-programmed configuration (frequency plan, output formats, voltage settings), making them drop-in replacements when the programmed features match the target application.

SI5334C-B05946-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334C-B05946-GMR FAQ

1.How can I place an order for SI5334C-B05946-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334C-B05946-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334C-B05946-GMR reliable?

The price and inventory of SI5334C-B05946-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B05946-GMR is usually 5 days.

3.What payment methods are accepted for SI5334C-B05946-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B05946-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334C-B05946-GMR?

SI5334C-B05946-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334C-B05946-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334C-B05946-GMR?

For technical support, including SI5334C-B05946-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B05946-GMR requirements.

6.How does Aetrix verify that SI5334C-B05946-GMR is sourced from the original manufacturer or authorized distributors?

All SI5334C-B05946-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B05946-GMR meets industry standards.

7.What is the process for return or replacement of SI5334C-B05946-GMR?

All SI5334C-B05946-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B05946-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334C-B05946-GMR part is unused and in its original packaging.

Return procedure for SI5334C-B05946-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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