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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334C-B09895-GM

Name: SI5334C-B09895-GM
Brand: Skyworks Solutions Inc.
SKU: SI5334C-B09895-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334C-B09895-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: -

Datasheet:: SI5334C-B09895-GM.pdf

Description:: IC CLOCK GENERATOR QUAD 24QFN

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Product details

Overview

SI5334C-B09895-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator IC with four independently configurable differential clock outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz per output using MultiSynth fractional-N PLL technology, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, and operates from 1.8/2.5/3.3 V core and output supply rails. It is deployed in PCIe 3.0 timing, FPGA clocking, and broadcast video systems requiring precise multi-output synchronization.

For engineers reviewing the SI5334C-B09895-GM datasheet, SI5334C-B09895-GM pinout, SI5334C-B09895-GM application, or SI5334C-B09895-GM equivalent, this page provides verified technical context, exact pin functions, real-world use scenarios, validated alternative options, and supply-chain support details specific to this factory-programmed variant of the Si5334 family.

Technical Context

The SI5334C-B09895-GM implements a two-stage synthesis architecture: a primary fractional-N PLL (phase detector, charge pump, loop filter, VCO) followed by four independent MultiSynth dividers - each capable of integer or fractional division to generate zero-ppm-error output frequencies. Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.

Each of the four differential output pairs (CLK0A/B through CLK3A/B) features independent voltage control (1.5/1.8/2.5/3.3 V), format selection, phase adjustment (<20 ps step, ±45 ns range), and glitchless frequency increment/decrement (1 ppm steps, up to 350 MHz). Loss-of-signal (LOSLOL) and optional zero-delay feedback mode further enable robust system-level timing control.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B); supports up to 8 single-ended clocks via internal termination
Frequency range per output	0.16–710 MHz (LVPECL/LVDS up to 350 MHz; HCSL up to 250 MHz; CMOS up to 200 MHz; SSTL/HSTL up to 350 MHz)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz, LVDS/HCSL/LVPECL outputs, low-noise differential input)
Core supply voltage	1.8 V, 2.5 V, or 3.3 V (±10% tolerance); 45 mA typical current at 100 MHz on all outputs, 25 MHz refclk
Output supply voltage per bank	VDDO0–VDDO3 independently configurable to 1.5 V, 1.8 V, 2.5 V, or 3.3 V for mixed-signal interface compatibility
Package & footprint	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad; RoHS-compliant, –40 °C to +85 °C operating range
Input reference options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) on dedicated pins IN1–IN7

Pinout & Package

SI5334C-B09895-GM is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with an exposed thermal pad. Pin assignments are fixed per the Si5334 family layout and validated for this B09895 configuration.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input (primary)	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference input	Supports 5–200 MHz CMOS-level input; VIH = 0.7×VDD, VIL = 0.3×VDD
IN5 / IN6	Differential feedback input (FDBK/FDBKB)	Enables zero-delay mode when connected to selected output; supports 5–710 MHz
IN7	Crystal input (XTAL/CLKIN)	Drives internal oscillator with 8–30 MHz fundamental-mode crystal; on-chip load capacitance 11–13 pF
CLK0A / CLK0B	Differential output 0	Factory-configured clock output; supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL; VDDO0 supplies driver
CLK1A / CLK1B	Differential output 1	Independent format/voltage/frequency; same capabilities as CLK0A/B; VDDO1 supplies driver
CLK2A / CLK2B	Differential output 2	Independent configuration; VDDO2 supplies driver; supports phase/frequency adjustment
CLK3A / CLK3B	Differential output 3	Independent configuration; VDDO3 supplies driver; supports spread spectrum (if enabled)
OEB	Output enable bar	Active-low global output disable; synchronous assertion prevents glitches during disable
LOSLOL	Loss-of-signal/loss-of-lock alarm	Open-drain output asserts low within 5 µs on loss of input signal or PLL lock
VDD	Core supply	1.8/2.5/3.3 V core rail; decoupling required per datasheet layout guidelines
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V rails per output bank; enables mixed-voltage system interfacing
GND / RSVD_GND	Ground connections	Multiple GND pins including dedicated ground for thermal pad; mandatory connection for thermal and noise performance

Key Features

Feature	Design Value
MultiSynth fractional-N synthesis	Four independent output dividers enabling zero-ppm frequency accuracy and sub-Hz resolution on each output
Per-output voltage & format control	Each of four output banks supports independent VDDO (1.5/1.8/2.5/3.3 V) and selectable logic format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL)
Glitchless frequency tuning	Pin-controlled frequency increment/decrement on CLK0A/B only, 1 ppm steps, up to 350 MHz, no output interruption
Sub-20 ps phase adjustment	Programmable initial phase offset and dynamic phase increment/decrement (±45 ns range, <20 ps step size) per output
PCIe 2.0-compliant spread spectrum	SSC available on any output ≥100 MHz with Rn divider = 1; ±0.5% deviation at 30–33 kHz modulation rate
Zero-delay feedback mode	Optional external feedback path via IN5/IN6 enables phase-aligned output-to-input tracking with null propagation delay

Applications

Ethernet Switch/Routing Timing	PCI Express 3.0 Clocking
Use Scenario: Synchronizing 10 GbE line cards with multi-rate SerDes PHYs requiring independent 156.25 MHz, 125 MHz, and 100 MHz clocks. IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, independently formatted outputs to drive multiple PHYs and MAC interfaces simultaneously. Use Value: Eliminates need for multiple discrete oscillators; reduces board area and power vs. dual-clock solutions while maintaining <0.7 ps RMS jitter compliance for IEEE 802.3ae.	Use Scenario: Generating compliant reference clocks for PCIe 3.0 root complex and endpoint devices in server backplanes. IC Role / Device Role / Timing Role: Supplies 100 MHz HCSL clocks meeting PCIe 3.0 common-clock jitter spec (≤0.45 ps RMS, 10 kHz–50 MHz). Use Value: Delivers measured 0.15–0.45 ps RMS jitter across all outputs; supports SSC for EMI reduction without violating PCIe jitter mask.
Broadcast Video/Audio Timing	FPGA & Processor Clocking
Use Scenario: Providing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks for SDI transceivers and audio sample-rate converters in broadcast encoders. IC Role / Device Role / Timing Role: Any-frequency synthesis engine generating exact SMPTE ST 292/ST 2081 rates with sub-ns inter-output skew. Use Value: Achieves <100 ps output-to-output skew and ±45 ns programmable phase alignment-critical for frame-accurate video switching and lip-sync audio paths.	Use Scenario: Driving high-speed I/O banks, memory controllers, and logic fabric of Xilinx Versal and Intel Agilex FPGAs with mixed-voltage clock domains. IC Role / Device Role / Timing Role: Configurable quad-output generator delivering 300 MHz LVDS for transceivers, 100 MHz HSTL for DDR4, and 50 MHz CMOS for management logic. Use Value: Independent VDDO per output enables direct interface to 1.2 V, 1.8 V, and 3.3 V I/O standards without level shifters; reduces BOM count and routing complexity.

Ethernet Switch/Routing Timing

PCI Express 3.0 Clocking

Use Scenario: Synchronizing 10 GbE line cards with multi-rate SerDes PHYs requiring independent 156.25 MHz, 125 MHz, and 100 MHz clocks.

IC Role / Device Role / Timing Role: Quad clock generator providing four low-jitter, independently formatted outputs to drive multiple PHYs and MAC interfaces simultaneously.

Use Value: Eliminates need for multiple discrete oscillators; reduces board area and power vs. dual-clock solutions while maintaining <0.7 ps RMS jitter compliance for IEEE 802.3ae.

Use Scenario: Generating compliant reference clocks for PCIe 3.0 root complex and endpoint devices in server backplanes.

IC Role / Device Role / Timing Role: Supplies 100 MHz HCSL clocks meeting PCIe 3.0 common-clock jitter spec (≤0.45 ps RMS, 10 kHz–50 MHz).

Use Value: Delivers measured 0.15–0.45 ps RMS jitter across all outputs; supports SSC for EMI reduction without violating PCIe jitter mask.

Broadcast Video/Audio Timing

FPGA & Processor Clocking

Use Scenario: Providing genlock-capable 27 MHz, 74.25 MHz, and 148.5 MHz clocks for SDI transceivers and audio sample-rate converters in broadcast encoders.

IC Role / Device Role / Timing Role: Any-frequency synthesis engine generating exact SMPTE ST 292/ST 2081 rates with sub-ns inter-output skew.

Use Value: Achieves <100 ps output-to-output skew and ±45 ns programmable phase alignment-critical for frame-accurate video switching and lip-sync audio paths.

Use Scenario: Driving high-speed I/O banks, memory controllers, and logic fabric of Xilinx Versal and Intel Agilex FPGAs with mixed-voltage clock domains.

IC Role / Device Role / Timing Role: Configurable quad-output generator delivering 300 MHz LVDS for transceivers, 100 MHz HSTL for DDR4, and 50 MHz CMOS for management logic.

Use Value: Independent VDDO per output enables direct interface to 1.2 V, 1.8 V, and 3.3 V I/O standards without level shifters; reduces BOM count and routing complexity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08885-GM	Higher integration: 8 outputs, integrated EEPROM, I²C programmability; lower jitter (0.5 ps RMS typ); larger 32-QFN package	Required for designs needing >4 outputs or field reconfiguration; not pin-compatible; higher cost and layout footprint	Select when future scalability, post-production tuning, or tighter jitter specs are required; avoid if pin count, size, or cost sensitivity dominates.
ICS853S02I2T	Fixed 2-output LVDS generator; no frequency synthesis (only divide-by-N); 1.2 ps RMS jitter; 16-TSSOP package	Limited to simple clock distribution; cannot synthesize arbitrary frequencies; no phase/frequency tuning or mixed-format support	Choose only for basic, low-cost clock fanout where frequency flexibility and advanced features are unnecessary.

Compared with Si5332A-D08885-GM, SI5334C-B09895-GM offers smaller footprint and simpler pin-control operation but lacks field reprogrammability; versus ICS853S02I2T, it provides full any-frequency synthesis and four independent outputs at higher precision, making it suitable for complex timing architectures where flexibility outweighs simplicity.

Availability

SI5334C-B09895-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe 3.0 clocking, and broadcast video/audio timing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5334C-B09895-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure, automotive, and industrial markets.

The SI5334C-B09895-GM belongs to Skyworks' Si5334 family of pin-controlled, any-frequency clock generators designed for high-density, low-jitter timing in networking, data center, and broadcast equipment where flexible multi-output synthesis replaces discrete oscillator arrays.

FAQ

What is the maximum output frequency supported by SI5334C-B09895-GM in LVPECL format?

The SI5334C-B09895-GM supports LVPECL output frequencies up to 710 MHz, as confirmed in Table 4 of the datasheet under "Output Clocks (Differential)" for LVPECL. This capability applies when the MultiSynth output frequency remains within the Fvco/8 limit (350 MHz) or uses select higher-frequency modes (367–473.33 MHz and 550–710 MHz bands), subject to proper layout and termination.

Does SI5334C-B09895-GM require an external I²C interface for configuration?

No, SI5334C-B09895-GM does not require an external I²C interface. It is factory-programmed with a fixed configuration stored in one-time-programmable (OTP) NVM and operates autonomously on power-up. All functional settings-including output frequencies, formats, voltages, and spread spectrum-are preloaded; pin strapping (e.g., OEB, LOSLOL) enables runtime control only.

Can SI5334C-B09895-GM generate different output formats simultaneously (e.g., LVDS and HCSL)?

Yes, SI5334C-B09895-GM supports simultaneous mixed-format outputs: each of the four differential output pairs (CLK0A/B through CLK3A/B) can be independently configured for LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL. This is enabled by per-output driver circuitry and independent VDDO supplies, allowing direct interface to heterogeneous system components without external level shifters.

What is the phase jitter performance of SI5334C-B09895-GM under PCIe 3.0 requirements?

SI5334C-B09895-GM delivers 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) in HCSL format at 100 MHz, fully compliant with the PCIe 3.0 common-clock jitter specification. This value is measured per AN562 and Intel Clock Jitter Tool v1.6.4, confirming suitability for root complex and endpoint timing in Gen3 and backward-compatible Gen2/Gen1 systems.

Is zero-delay mode supported on SI5334C-B09895-GM, and how is it implemented?

Yes, zero-delay mode is supported on SI5334C-B09895-GM. It is implemented by routing one of the device's differential outputs (e.g., CLK0A/B) to the FDBK/FDBKB pins (IN5/IN6), closing the PLL feedback path externally. This eliminates static phase offset between reference input and that output, enabling deterministic phase alignment critical for clock forwarding and retiming applications.

SI5334C-B09895-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: *

Package/Case:: -

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

SI5334C-B09895-GM FAQ

1.How can I place an order for SI5334C-B09895-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334C-B09895-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334C-B09895-GM reliable?

The price and inventory of SI5334C-B09895-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334C-B09895-GM is usually 5 days.

3.What payment methods are accepted for SI5334C-B09895-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334C-B09895-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334C-B09895-GM?

SI5334C-B09895-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334C-B09895-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334C-B09895-GM?

For technical support, including SI5334C-B09895-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334C-B09895-GM requirements.

6.How does Aetrix verify that SI5334C-B09895-GM is sourced from the original manufacturer or authorized distributors?

All SI5334C-B09895-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334C-B09895-GM meets industry standards.

7.What is the process for return or replacement of SI5334C-B09895-GM?

All SI5334C-B09895-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334C-B09895-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334C-B09895-GM part is unused and in its original packaging.

Return procedure for SI5334C-B09895-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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