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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334J-B05589-GM

Name: SI5334J-B05589-GM
Brand: Skyworks Solutions Inc.
SKU: SI5334J-B05589-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334J-B05589-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334J-B05589-GM.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334J-B05589-GM from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz per output using MultiSynth fractional-N synthesis, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL formats, and operates from 1.8/2.5/3.3 V core and output supplies - deployed in PCIe 3.0 timing, FPGA clocking, and broadcast video systems.

For engineers reviewing the SI5334J-B05589-GM datasheet, SI5334J-B05589-GM pinout, SI5334J-B05589-GM application, or SI5334J-B05589-GM equivalent, key selection considerations include its 4× independent output flexibility, factory-programmed configuration, zero-ppm frequency accuracy, pin-controlled frequency increment/decrement (1 ppm steps on CLK0A/B), and 4×4 mm 24-QFN package with integrated loss-of-signal/loss-of-lock monitoring.

Technical Context

The SI5334J-B05589-GM implements a two-stage synthesis architecture: a primary fractional-N PLL (phase detector, charge pump, loop filter, VCO) followed by four independent MultiSynth dividers enabling non-integer frequency synthesis per output. It accepts input references from 5–710 MHz (differential), 5–350 MHz (SSTL/HSTL), 5–200 MHz (CMOS), or 8–30 MHz crystals.

Each of the four differential outputs supports independent signal format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), independent output supply voltage (1.5/1.8/2.5/3.3 V), and independent phase offset (±45 ns in <20 ps steps). The J-suffix variant specifically enables pin-controlled frequency increment/decrement on CLK0A/B only, with glitchless 1 ppm step size and up to 350 MHz range.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count & Type	4 differential clock outputs, each independently configurable for frequency, format, and voltage
Frequency Range	0.16–710 MHz per output; integer/fractional synthesis with zero ppm error
Phase Jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe 3.0 and GbE jitter requirements
Core Supply Voltage	1.8 V, 2.5 V, or 3.3 V - supports mixed-voltage system integration
Package	4 × 4 mm, 24-pin QFN - space-efficient for high-density timing applications
Operating Temperature	–40 °C to +85 °C - qualified for industrial and telecom environments
Control Interface	Pin-controlled only (no I²C); includes OEB (output enable), LOSLOL (alarm), and FDEC/FINC pins

Pinout & Package

SI5334J-B05589-GM is housed in a 4 × 4 mm, 24-lead QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5334 family layout and validated for this specific variant.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential Output Pair 0	Primary output pair supporting frequency increment/decrement (FDEC/FINC) in J-suffix devices
CLK1A / CLK1B	Differential Output Pair 1	Fully configurable output; no pin-controlled freq/phase adjustment in J variant
CLK2A / CLK2B	Differential Output Pair 2	Fully configurable output; independent format/voltage settings
CLK3A / CLK3B	Differential Output Pair 3	Fully configurable output; supports HCSL/LVDS/LVPECL up to 250/350/710 MHz respectively
IN1 / IN2	Differential Reference Input	Accepts 5–710 MHz AC-coupled differential clock (e.g., LVDS, LVPECL)
IN3 / IN4	Single-Ended Reference Input	Accepts 5–200 MHz CMOS-level clock; VIH = 0.7×VDD, VIL = 0.3×VDD
IN5 / IN6	Secondary Differential Input	Redundant or alternate reference path; identical spec to IN1/IN2
IN7	Crystal Input (XTAL)	Supports 8–30 MHz fundamental-mode crystal with on-chip 12 pF load capacitance
VDD	Core Supply	1.8/2.5/3.3 V supply for PLL and logic; max 60 mA current draw
VDDO0–VDDO3	Output Buffer Supplies	Independent 1.5/1.8/2.5/3.3 V supplies per output pair - enables mixed-signal interfacing
OEB	Output Enable Bar	Active-low global output disable; places all outputs in high-Z state
LOSLOL	Loss-of-Signal/Loss-of-Lock Alarm	Open-drain output asserting low on input failure or PLL unlock (2.6–5 µs response)
RSVD_GND	Reserved Ground	Internally connected to die ground; must be tied to PCB ground plane
GND	Power Ground	Primary ground connection; ties to exposed thermal pad

Key Features

Feature	Design Value
MultiSynth Fractional-N Synthesis	Enables any-frequency generation per output with zero ppm error and <0.7 ps RMS jitter
Pin-Controlled Frequency Adjustment	Glitchless ±1 ppm step increments/decrements on CLK0A/B only - no firmware or I²C required
Independent Output Configuration	Each output supports unique format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5–3.3 V), and termination
Factory-Programmed Operation	Pre-configured at manufacture; powers up immediately in defined state - no host initialization needed
Integrated Monitoring	Hardware-based LOSLOL alarm detects input loss or PLL unlock within 5 µs - critical for telecom fail-safe timing
Zero-Delay Mode Support	Optional external feedback path (FDBK/FDBKB) enables phase-aligned output-to-input tracking for clock forwarding

Applications

PCI Express 3.0 Timing	FPGA & ASIC Clock Distribution
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe 3.0 endpoints and root complexes in server backplanes. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) 100 MHz HCSL clocks compliant with PCIe 3.0 jitter mask. Use Value: Eliminates need for multiple discrete oscillators; enables single-device timing solution with guaranteed 0 ppm frequency accuracy and spread-spectrum support.	Use Scenario: Driving heterogeneous clock domains in Xilinx Versal or Intel Agilex FPGAs requiring 156.25 MHz GTY transceiver clocks, 100 MHz fabric clocks, and 200 MHz DDR4 memory clocks. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three distinct frequencies simultaneously with independent voltage and format control per output. Use Value: Reduces BOM count and board area; avoids external level shifters via per-output VDDO pins (1.8 V for GTY, 2.5 V for DDR4, 3.3 V for legacy peripherals).
Broadcast Video Timing	Telecom Line Card Synchronization
Use Scenario: Generating SMPTE ST 2082 (12G-SDI) 297 MHz clock and ancillary 74.25 MHz/148.5 MHz video clocks in professional video switchers. IC Role / Device Role / Timing Role: High-stability clock generator delivering sub-1 ps RMS jitter outputs meeting SMPTE jitter compliance for 12G-SDI physical layer. Use Value: Supports multi-rate video timing without external PLLs; leverages MultiSynth's wide frequency range (0.16–710 MHz) and low deterministic jitter (<10 ps pk-pk).	Use Scenario: Providing E1/T1 framing clocks (2.048 MHz/1.544 MHz), SyncE Ethernet clocks (156.25 MHz), and processor clocks (200 MHz) in carrier-grade line cards. IC Role / Device Role / Timing Role: Multi-protocol timing hub accepting Stratum-3 OCXO input and generating telecom-grade clocks with holdover stability and LOSLOL alarm. Use Value: Replaces discrete clock ICs and crystal oscillators; simplifies PTP/1588 synchronization architecture with deterministic phase alignment across outputs.

PCI Express 3.0 Timing

FPGA & ASIC Clock Distribution

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe 3.0 endpoints and root complexes in server backplanes.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter (≤0.45 ps RMS) 100 MHz HCSL clocks compliant with PCIe 3.0 jitter mask.

Use Value: Eliminates need for multiple discrete oscillators; enables single-device timing solution with guaranteed 0 ppm frequency accuracy and spread-spectrum support.

Use Scenario: Driving heterogeneous clock domains in Xilinx Versal or Intel Agilex FPGAs requiring 156.25 MHz GTY transceiver clocks, 100 MHz fabric clocks, and 200 MHz DDR4 memory clocks.

IC Role / Device Role / Timing Role: Any-frequency synthesizer generating three distinct frequencies simultaneously with independent voltage and format control per output.

Use Value: Reduces BOM count and board area; avoids external level shifters via per-output VDDO pins (1.8 V for GTY, 2.5 V for DDR4, 3.3 V for legacy peripherals).

Broadcast Video Timing

Telecom Line Card Synchronization

Use Scenario: Generating SMPTE ST 2082 (12G-SDI) 297 MHz clock and ancillary 74.25 MHz/148.5 MHz video clocks in professional video switchers.

IC Role / Device Role / Timing Role: High-stability clock generator delivering sub-1 ps RMS jitter outputs meeting SMPTE jitter compliance for 12G-SDI physical layer.

Use Value: Supports multi-rate video timing without external PLLs; leverages MultiSynth's wide frequency range (0.16–710 MHz) and low deterministic jitter (<10 ps pk-pk).

Use Scenario: Providing E1/T1 framing clocks (2.048 MHz/1.544 MHz), SyncE Ethernet clocks (156.25 MHz), and processor clocks (200 MHz) in carrier-grade line cards.

IC Role / Device Role / Timing Role: Multi-protocol timing hub accepting Stratum-3 OCXO input and generating telecom-grade clocks with holdover stability and LOSLOL alarm.

Use Value: Replaces discrete clock ICs and crystal oscillators; simplifies PTP/1588 synchronization architecture with deterministic phase alignment across outputs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05589-GM	Higher integration: dual PLL, 10 outputs, I²C programmability; 0.35 ps RMS jitter; supports JESD204B deterministic latency	Required for multi-PLL architectures, JESD204B baseband, or >4 output needs; not pin-compatible	Select when system demands programmable configuration, ultra-low jitter, or >4 outputs - requires firmware integration and layout redesign
ICS853S01AG-01T	Fixed-frequency, 4-output LVDS generator; no frequency synthesis; 1.2 ps RMS jitter; 3.3 V only; no phase/freq adjustment	Suitable only for static clock trees with predefined frequencies; lacks any-frequency capability and voltage flexibility	Choose for cost-sensitive, low-complexity designs where all clocks are fixed and jitter ≤1.2 ps RMS is acceptable

Compared with SI5334J-B05589-GM, the Si5332A offers superior jitter and configurability but requires I²C infrastructure and board rework, while the ICS853S01AG provides lower cost and simplicity at the expense of synthesis flexibility and multi-voltage support.

Availability

SI5334J-B05589-GM is available at Aetrix Electronics and suitable for PCIe 3.0 timing, FPGA clock distribution, and broadcast video applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5334J-B05589-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si5334 product line delivers pin-controlled, any-frequency clock generation for high-speed digital systems - designed to replace multiple oscillators and simplify timing architecture in networking, computing, and communications equipment.

FAQ

What is the maximum output frequency supported by SI5334J-B05589-GM?

The SI5334J-B05589-GM supports up to 710 MHz on LVPECL outputs, 350 MHz on LVDS/SSTL/HSTL, 250 MHz on HCSL, and 200 MHz on CMOS. These limits are format-dependent and verified per Skyworks datasheet Table 4. The J-suffix device maintains full frequency capability across all outputs, with frequency increment/decrement restricted to CLK0A/B only.

Does SI5334J-B05589-GM require I²C programming or configuration at power-up?

No. SI5334J-B05589-GM is factory-programmed with OTP NVM and powers up immediately in its predefined configuration - no host processor, I²C interface, or firmware initialization is required. All settings (frequencies, formats, voltages, phase offsets) are stored permanently and active on POR.

Can SI5334J-B05589-GM generate different output voltages simultaneously?

Yes. SI5334J-B05589-GM provides four independent VDDOx pins (VDDO0–VDDO3), each configurable for 1.5 V, 1.8 V, 2.5 V, or 3.3 V. This allows simultaneous LVDS (2.5 V), HCSL (1.8 V), and CMOS (3.3 V) outputs - essential for interfacing with mixed-voltage FPGAs, SerDes, and memory interfaces.

What input reference options does SI5334J-B05589-GM support?

SI5334J-B05589-GM accepts an 8–30 MHz fundamental-mode crystal on IN7, or single-ended CMOS (5–200 MHz on IN3/IN4), or differential inputs (5–710 MHz on IN1/IN2 or IN5/IN6). Input voltage thresholds are rail-relative (VIH = 0.7×VDD), and slew rate requirements (≥1 V/ns for CMOS, ≥0.3 V/ns for differential) are specified for optimal jitter performance.

Is SI5334J-B05589-GM compatible with PCIe 3.0 jitter specifications?

Yes. SI5334J-B05589-GM delivers ≤0.45 ps RMS jitter (10 kHz–50 MHz) in PCIe 3.0 common-clocked mode per Table 10, meeting the 1.0 ps RMS requirement with margin. Tested with 100 MHz HCSL outputs and validated using Intel Clock Jitter Tool v1.6.4 per AN562 methodology.

SI5334J-B05589-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334J-B05589-GM FAQ

1.How can I place an order for SI5334J-B05589-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334J-B05589-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334J-B05589-GM reliable?

The price and inventory of SI5334J-B05589-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334J-B05589-GM is usually 5 days.

3.What payment methods are accepted for SI5334J-B05589-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334J-B05589-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334J-B05589-GM?

SI5334J-B05589-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334J-B05589-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334J-B05589-GM?

For technical support, including SI5334J-B05589-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334J-B05589-GM requirements.

6.How does Aetrix verify that SI5334J-B05589-GM is sourced from the original manufacturer or authorized distributors?

All SI5334J-B05589-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334J-B05589-GM meets industry standards.

7.What is the process for return or replacement of SI5334J-B05589-GM?

All SI5334J-B05589-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334J-B05589-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334J-B05589-GM part is unused and in its original packaging.

Return procedure for SI5334J-B05589-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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