Skyworks Solutions Inc. SI5334K-B04338-GM
- Part No.:
- SI5334K-B04338-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5334K-B04338-GM.pdf
- Description:
- 4-OUTPUT, ANY FREQUENCY(<710MHZ)
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5334K-B04338-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, 0 ppm frequency accuracy, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats up to 710 MHz. It operates from 1.8/2.5/3.3 V core supply and targets PCIe 2.0/3.0, Ethernet switch/router, and FPGA clocking applications.
For engineers reviewing the SI5334K-B04338-GM datasheet, SI5334K-B04338-GM pinout, SI5334K-B04338-GM application, or SI5334K-B04338-GM equivalent, this page delivers verified specifications, package mapping, functional pin roles, real-world use cases, and validated alternative options - all grounded in Skyworks' official Si5334 Rev. 1.3 documentation.
Technical Context
The SI5334K-B04338-GM implements a fractional-N PLL architecture with integrated VCO and four independent MultiSynth synthesis stages, each supporting non-integer frequency division to generate arbitrary output frequencies. Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.
Each of the four differential output pairs (CLK0A/B through CLK3A/B) features independent voltage control (1.5/1.8/2.5/3.3 V), format selection, phase adjustment (<20 ps steps over ±45 ns), and glitchless frequency increment/decrement (1 ppm steps, up to 350 MHz). Spread spectrum is PCI Express 2.0 compliant on 100 MHz outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential clock outputs (CLK0A/B to CLK3A/B), each independently configurable |
| Frequency range | 0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS with integer-related constraints |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), enabling compliance with PCIe 3.0 and 10 GbE timing budgets |
| Frequency accuracy | True 0 ppm error across all outputs due to MultiSynth fractional synthesis |
| Supply voltages | Core: 1.8/2.5/3.3 V; Output buffers: 1.5/1.8/2.5/3.3 V - supports mixed-voltage system interfacing |
| Input reference | Crystal (8–30 MHz) or AC/DC-coupled clock (5–710 MHz), with loss-of-signal detection |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient for high-density PCBs |
Pinout & Package
SI5334K-B04338-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments follow Skyworks' standardized Si5334 top-view layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1 / IN2 | Differential reference input (P/N) | Accepts 5–710 MHz AC-coupled differential clock; internal 10 kΩ termination |
| IN3 / IN4 | Single-ended reference input (P/N) | Supports 5–200 MHz CMOS/SSTL/HSTL; VIH = 0.7×VDD, VIL = 0.3×VDD |
| CLK0A / CLK0B | Differential output pair 0 | Programmable format/voltage; supports phase/frequency adjustment via PINC/FINC |
| CLK1A / CLK1B | Differential output pair 1 | Independent format/voltage; no frequency increment/decrement (K variant feature limited to CLK0) |
| CLK2A / CLK2B | Differential output pair 2 | Configurable for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL; 0.16–350 MHz base range |
| CLK3A / CLK3B | Differential output pair 3 | Same configurability as CLK2; supports spread spectrum when set to 100 MHz |
| VDDO0–VDDO3 | Output buffer supplies | Independent 1.5/1.8/2.5/3.3 V per output pair - enables mixed-signal interface without level shifters |
| VDD | Core supply | 1.8/2.5/3.3 V ±10%; IDD = 45 mA typ at 100 MHz outputs + 25 MHz refclk |
| LOSLOL | Loss-of-signal/loss-of-lock alarm | Open-drain active-low output; asserts within 5 µs of input failure or PLL unlock |
| OEB | Output enable bar | Active-low global enable; disables all outputs simultaneously with <2 ns propagation delay |
| RSVD_GND | Reserved ground | Internally connected to substrate; must be tied to PCB ground plane |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth frequency synthesis | Enables zero-ppm arbitrary-frequency generation on all four outputs without external loop filters or VCO tuning |
| Independent output voltage per driver | Eliminates need for external level shifters when driving mixed-voltage FPGAs, ASICs, or SerDes blocks |
| Pin-controlled frequency increment/decrement | Allows real-time, glitchless clock margining at 1 ppm resolution on CLK0A/B - critical for production test and reliability validation |
| PCIe 2.0-compliant spread spectrum | Reduces EMI on 100 MHz outputs without violating PCIe jitter masks (RMS ≤ 0.45 ps) |
| Phase adjustment with <20 ps resolution | Enables precise skew alignment between high-speed parallel buses (e.g., DDR memory interfaces or multi-lane SerDes) |
Applications
| Ethernet Switch/Router Timing | PCI Express 2.0/3.0 Clocking |
|---|---|
Use Scenario: Synchronizing packet processing units, MAC layers, and PHY transceivers in Layer 2/3 switches and routers operating at 1 GbE/10 GbE line rates. IC Role / Device Role / Timing Role: Quad-output clock generator providing independent, low-jitter clocks for CPU, switch fabric, SerDes, and management controller. Use Value: 0.7 ps RMS jitter ensures compliance with IEEE 802.3ae and PCIe 3.0 jitter budgets; pin-controlled frequency margining validates timing closure under voltage/temperature corners. |
Use Scenario: Delivering reference clocks to root complex, endpoint devices, and switch chips in server, storage, and AI accelerator platforms. IC Role / Device Role / Timing Role: Primary clock source generating 100 MHz REFCLK, 125 MHz QPI, and auxiliary clocks for PCIe Gen2/Gen3 lanes. Use Value: Spread spectrum on 100 MHz outputs reduces EMI without violating PCIe common-clock TJ limits; 0 ppm accuracy prevents link training failures. |
| FPGA & Processor Clocking | Broadcast Video/Audio Timing |
Use Scenario: Supplying multiple synchronous clocks to heterogeneous FPGA logic regions (e.g., video pipeline, DDR controller, PCIe core) and companion processors. IC Role / Device Role / Timing Role: Configurable quad clock generator delivering distinct frequencies and formats (LVDS for DDR, HCSL for PCIe, CMOS for peripherals). Use Value: Independent VDDO per output allows direct connection to 1.2 V, 1.8 V, and 3.3 V I/O banks; phase adjustment aligns setup/hold margins across clock domains. |
Use Scenario: Generating SMPTE-compliant timing signals (e.g., 27 MHz, 74.25 MHz, 148.5 MHz) for SDI serializers, video encoders, and audio sample-rate converters. IC Role / Device Role / Timing Role: Precision clock synthesizer replacing multiple fixed-frequency oscillators with one programmable device. Use Value: MultiSynth's 0 ppm accuracy eliminates frame sync drift; low deterministic jitter (<10 ps pk-pk) prevents video artifacts in 4K/8K broadcast chains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D08989-GM | Higher integration: 8 outputs, integrated EEPROM, I²C programmability; 0.5 ps RMS jitter; supports JESD204B deterministic latency | Required for systems needing >4 outputs or dynamic reconfiguration; not pin-compatible | Select when field-upgradable configuration or sub-0.7 ps jitter is mandatory; SI5334K-B04338-GM remains optimal for cost-sensitive, pin-controlled 4-output designs |
| ICS8430I-01T | Fixed-frequency quad LVDS generator (100/125/156.25/200 MHz); no frequency synthesis; 1.2 ps RMS jitter; 3.3 V only | Limited to predefined frequencies; no spread spectrum or phase adjustment | Choose only for legacy designs locked to standard frequencies where programmability is unnecessary and lower BOM cost outweighs flexibility |
Compared with Si5332A-D08989-GM and ICS8430I-01T, SI5334K-B04338-GM uniquely balances factory-programmed simplicity, pin-based real-time control, and full any-frequency synthesis - making it ideal for PCIe- and Ethernet-focused designs requiring guaranteed 0 ppm accuracy without firmware overhead.
Availability
SI5334K-B04338-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe 2.0/3.0 clocking, and FPGA processor clocking applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SI5334K-B04338-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure, automotive, and mobile markets.
The SI5334K-B04338-GM belongs to Skyworks' Si533x family of any-frequency clock generators, designed specifically for high-performance, low-jitter timing in datacenter, telecom, and broadcast systems where flexible, deterministic clock synthesis is critical.
FAQ
What is the maximum output frequency supported by SI5334K-B04338-GM?
The SI5334K-B04338-GM supports up to 710 MHz on LVPECL/LVDS outputs when using integer-related synthesis paths, but the guaranteed full-range operation across all formats is 0.16–350 MHz. Frequencies above 350 MHz require specific MultiSynth divider configurations and are subject to Fvco/8 constraints per Skyworks Rev. 1.3 documentation.
Does SI5334K-B04338-GM support spread spectrum clocking?
Yes - SI5334K-B04338-GM supports PCI Express 2.0-compliant spread spectrum on any output clock configured to 100 MHz with Rn divider = 1. The modulation rate is 30–33 kHz with ±0.5% frequency deviation, reducing EMI without violating PCIe jitter specifications.
Can SI5334K-B04338-GM generate different output formats simultaneously?
Yes - SI5334K-B04338-GM supports simultaneous LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL outputs. Each of the four differential output pairs (CLK0A/B through CLK3A/B) can be independently assigned a signal format and output supply voltage (1.5/1.8/2.5/3.3 V).
What is the function of the LOSLOL pin on SI5334K-B04338-GM?
The LOSLOL pin on SI5334K-B04338-GM is an open-drain, active-low alarm that asserts within 5 µs of input clock loss or PLL loss-of-lock. It provides system-level fault detection without requiring external monitoring circuitry, simplifying power-on self-test and runtime health checks for SI5334K-B04338-GM deployments.
Is SI5334K-B04338-GM pin-compatible with other Si5334 variants?
Yes - all Si5334 variants, including SI5334K-B04338-GM, share identical 24-QFN packaging, pinout, and electrical interface. Differences lie in factory-programmed configuration (e.g., frequency plan, output format, spread spectrum enable), not physical or logical pin behavior.
SI5334K-B04338-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5334K-B04338-GM FAQ
1.How can I place an order for SI5334K-B04338-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5334K-B04338-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5334K-B04338-GM reliable?
The price and inventory of SI5334K-B04338-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334K-B04338-GM is usually 5 days.
3.What payment methods are accepted for SI5334K-B04338-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334K-B04338-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5334K-B04338-GM?
SI5334K-B04338-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5334K-B04338-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5334K-B04338-GM?
For technical support, including SI5334K-B04338-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334K-B04338-GM requirements.
6.How does Aetrix verify that SI5334K-B04338-GM is sourced from the original manufacturer or authorized distributors?
All SI5334K-B04338-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334K-B04338-GM meets industry standards.
7.What is the process for return or replacement of SI5334K-B04338-GM?
All SI5334K-B04338-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334K-B04338-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5334K-B04338-GM part is unused and in its original packaging.
Return procedure for SI5334K-B04338-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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