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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334K-B04338-GMR

Name: SI5334K-B04338-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5334K-B04338-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334K-B04338-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334K-B04338-GMR.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<710MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334K-B04338-GMR from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs, 0.7 ps RMS typical phase jitter, 350 MHz maximum integer-output frequency (up to 710 MHz at select frequencies), and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats in telecom, PCIe 2.0/3.0, and FPGA clocking applications.

For engineers reviewing the SI5334K-B04338-GMR datasheet, SI5334K-B04338-GMR pinout, SI5334K-B04338-GMR application, or SI5334K-B04338-GMR equivalent, key selection considerations include its factory-programmed configuration, 4×4 mm 24-QFN package, 1.8/2.5/3.3 V core supply compatibility, spread-spectrum capability on 100 MHz outputs, and loss-of-signal/loss-of-lock alarm functionality.

Technical Context

The SI5334K-B04338-GMR implements a fractional-N PLL with integrated VCO and four independent MultiSynth synthesis stages, each driving one of four differential output channels. Input flexibility includes crystal (8–30 MHz) or differential/single-ended clock inputs (5–710 MHz), with zero ppm frequency error across all outputs via patented MultiSynth technology.

Each output supports independent voltage rail selection (1.5/1.8/2.5/3.3 V), format selection, and phase adjustment (<20 ps step resolution over ±45 ns range). The K variant specifically enables PCI Express 2.0-compliant spread spectrum on any or all 100 MHz outputs and supports glitchless 1 ppm frequency increment/decrement on CLK0A/B only.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs, each independently configurable - enables multi-domain clocking without external fanout buffers
Max output frequency	350 MHz (integer mode), up to 710 MHz (select frequencies) - covers PCIe Gen3 (100 MHz), 10GbE (156.25 MHz), and Fibre Channel (212.5 MHz)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz) - meets stringent requirements for SerDes PHYs and high-speed ADCs
Frequency accuracy	0 ppm error - eliminates need for post-synthesis calibration or trimming in production systems
Supply voltages	Core: 1.8/2.5/3.3 V; Output buffers: 1.5/1.8/2.5/3.3 V - supports mixed-voltage SoC/FPGA interfaces
Package	24-pin QFN, 4 × 4 mm, 0.5 mm pitch - compact footprint compatible with dense PCB layouts and thermal constraints
Operating temperature	–40 °C to +85 °C - qualified for industrial and telecom line-card environments

Pinout & Package

SI5334K-B04338-GMR is housed in a 24-lead QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad. Pin assignments follow Skyworks' standard Si5334 pinout: dual differential input pairs (IN1/IN2, IN5/IN6), single-ended inputs (IN3, IN4), four differential output pairs (CLK0A/CLK0B through CLK3A/CLK3B), dedicated control pins (OEB, LOSLOL), and multiple VDD/VDDO rails.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input	Accepts 5–710 MHz AC-coupled differential clock; internal 100 Ω termination enables direct connection to LVDS/HCSL sources
IN3 / IN4	Single-ended reference input	Supports CMOS/SSTL/HSTL clocks (5–350 MHz); VIH/VIL thresholds scale with VDD for robust logic-level compatibility
CLK0A / CLK0B – CLK3A / CLK3B	Differential clock outputs	Four independent outputs; each configurable for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL with per-output VDDO rail
OEB	Output enable bar	Active-low global output disable; synchronous assertion prevents glitches during power sequencing or fault conditions
LOSLOL	Loss-of-signal/loss-of-lock indicator	Open-drain output asserts low on input clock failure or PLL unlock; supports system-level fault monitoring without MCU polling
VDD, VDDO0–VDDO3	Power supply terminals	Separate core (VDD) and per-output buffer (VDDOx) supplies allow mixed-voltage operation and noise isolation between domains

Key Features

Feature	Design Value
MultiSynth frequency synthesis	Independent any-frequency generation per output with zero ppm error - eliminates external PLLs and simplifies BOM for multi-clock systems
Spread spectrum (SSC)	PCIe 2.0-compliant SSC on 100 MHz outputs - reduces EMI peak amplitude without requiring host software control
Phase adjustment	±45 ns range with <20 ps step resolution - enables precise skew alignment across high-speed parallel buses (e.g., DDR, parallel video)
Frequency increment/decrement	Glitchless 1 ppm steps on CLK0A/B - supports margin testing, dynamic frequency tuning, and jitter characterization without reprogramming
Input flexibility	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), differential (5–710 MHz) - accommodates legacy and next-gen timing sources
Alarm signaling	Dedicated LOSLOL pin with fast response (2.6 µs assert time) - enables real-time system health monitoring in carrier-grade equipment

Applications

Ethernet Switch/Routing	PCI Express 2.0/3.0
Use Scenario: Synchronizing packet forwarding engines, MAC layers, and PHY interfaces in Layer 3 switches with multiple speed classes (1G/10G/25G). IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz clocks to switch fabric, PCIe root complex, and management controller. Use Value: Eliminates inter-clock skew and jitter accumulation across domains; 0.7 ps RMS jitter ensures compliance with IEEE 802.3bj KR/KR4 and PCIe Gen3 eye diagram masks.	Use Scenario: Clocking CPU, GPU, and storage controllers in servers with mixed PCIe Gen2/Gen3 endpoints. IC Role / Device Role / Timing Role: Generates 100 MHz PCIe reference clocks with SSC enabled on all outputs to meet FCC Class A radiated emissions limits. Use Value: Single-device solution replaces discrete oscillators and fanout buffers; spread spectrum reduces 100 MHz harmonic peaks by >10 dBμV/m without firmware overhead.
Broadcast Video/Audio Timing	Processor and FPGA Clocking
Use Scenario: Master timing source for SMPTE ST 2082 (12G-SDI) and AES67 audio-over-IP systems requiring sub-100 ps inter-channel skew. IC Role / Device Role / Timing Role: Delivers synchronized 27 MHz, 74.25 MHz, and 148.5 MHz LVDS clocks to video encoders, audio DSPs, and transport processors. Use Value: Phase-adjustable outputs align pixel clock edges across multi-lane serializers; 0.7 ps jitter preserves 12-bit ENOB in high-dynamic-range video ADCs.	Use Scenario: Providing startup and runtime clocks to Xilinx Versal ACAP and Intel Agilex FPGAs with mixed I/O bank voltages. IC Role / Device Role / Timing Role: Supplies 100 MHz configuration clock, 300 MHz transceiver reference, and 50 MHz system management clock with independent VDDO rails. Use Value: Per-output voltage control matches FPGA I/O standards (LVDS 2.5 V, HSTL 1.5 V, CMOS 1.8 V); eliminates level-shifters and reduces board area.

Ethernet Switch/Routing

PCI Express 2.0/3.0

Use Scenario: Synchronizing packet forwarding engines, MAC layers, and PHY interfaces in Layer 3 switches with multiple speed classes (1G/10G/25G).

IC Role / Device Role / Timing Role: Quad-output clock generator providing independent 125 MHz, 156.25 MHz, and 250 MHz clocks to switch fabric, PCIe root complex, and management controller.

Use Value: Eliminates inter-clock skew and jitter accumulation across domains; 0.7 ps RMS jitter ensures compliance with IEEE 802.3bj KR/KR4 and PCIe Gen3 eye diagram masks.

Use Scenario: Clocking CPU, GPU, and storage controllers in servers with mixed PCIe Gen2/Gen3 endpoints.

IC Role / Device Role / Timing Role: Generates 100 MHz PCIe reference clocks with SSC enabled on all outputs to meet FCC Class A radiated emissions limits.

Use Value: Single-device solution replaces discrete oscillators and fanout buffers; spread spectrum reduces 100 MHz harmonic peaks by >10 dBμV/m without firmware overhead.

Broadcast Video/Audio Timing

Processor and FPGA Clocking

Use Scenario: Master timing source for SMPTE ST 2082 (12G-SDI) and AES67 audio-over-IP systems requiring sub-100 ps inter-channel skew.

IC Role / Device Role / Timing Role: Delivers synchronized 27 MHz, 74.25 MHz, and 148.5 MHz LVDS clocks to video encoders, audio DSPs, and transport processors.

Use Value: Phase-adjustable outputs align pixel clock edges across multi-lane serializers; 0.7 ps jitter preserves 12-bit ENOB in high-dynamic-range video ADCs.

Use Scenario: Providing startup and runtime clocks to Xilinx Versal ACAP and Intel Agilex FPGAs with mixed I/O bank voltages.

IC Role / Device Role / Timing Role: Supplies 100 MHz configuration clock, 300 MHz transceiver reference, and 50 MHz system management clock with independent VDDO rails.

Use Value: Per-output voltage control matches FPGA I/O standards (LVDS 2.5 V, HSTL 1.5 V, CMOS 1.8 V); eliminates level-shifters and reduces board area.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06189-GM	Higher integration: 8 outputs, I²C programmability, lower jitter (0.35 ps RMS), but larger 32-QFN package	Requires firmware initialization; better suited for dynamically reconfigured systems (e.g., software-defined radio)	Select when field reconfiguration, higher channel count, or ultra-low jitter are required - not pin-compatible
ICS8430I-01T	Fixed-frequency 4-output LVDS generator; no frequency synthesis, no spread spectrum, 1.2 ps RMS jitter	Limited to pre-defined frequencies; no phase/frequency tuning; simpler layout but inflexible for multi-standard designs	Select for cost-sensitive, static-clocking applications where synthesis flexibility is unnecessary

Compared with Si5332A-D06189-GM, SI5334K-B04338-GMR offers factory-programmed simplicity and smaller footprint but lacks I²C control; versus ICS8430I-01T, it delivers full any-frequency synthesis and PCIe-compliant SSC at the cost of higher design complexity and price.

Availability

SI5334K-B04338-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router, PCIe 2.0/3.0, broadcast video/audio timing, processor and FPGA clocking, and telecom line card applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for SI5334K-B04338-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad portfolio coverage and high-reliability manufacturing.

The Si5334 family is designed for high-performance, low-jitter clock generation in datacenter, telecom, and broadcast systems where deterministic timing, multi-format flexibility, and EMI reduction are critical.

FAQ

What is the primary function of the SI5334K-B04338-GMR in a system?

The SI5334K-B04338-GMR serves as a quad-output, any-frequency clock generator that synthesizes four independent, low-jitter differential clock signals from a single reference input. Its core function is to replace multiple discrete oscillators and fanout buffers in systems requiring precise, flexible timing - such as PCIe root complexes, Ethernet switches, and FPGA-based platforms - while maintaining 0 ppm frequency accuracy and sub-1 ps RMS jitter. SI5334K-B04338-GMR achieves this using Skyworks' patented MultiSynth architecture with integrated fractional-N PLL and four synthesis stages.

Does the SI5334K-B04338-GMR support spread spectrum clocking, and under what conditions?

Yes, the SI5334K-B04338-GMR supports PCI Express 2.0-compliant spread spectrum clocking (SSC) on any or all output clocks, but only when the output frequency is exactly 100 MHz and the corresponding Rn divider is set to 1. This capability is specific to the "K" variant (as indicated in the part number suffix) and is implemented entirely in hardware - no I²C or firmware control is required. SI5334K-B04338-GMR delivers ±0.5% frequency deviation at 30–33 kHz modulation rate, reducing EMI peak emissions without affecting system timing margins.

Can the SI5334K-B04338-GMR generate frequencies above 350 MHz, and if so, how?

Yes, the SI5334K-B04338-GMR can generate output frequencies up to 710 MHz, but only at select frequencies determined by the underlying VCO and MultiSynth architecture - specifically, outputs at Fvco/4 and Fvco/6 (e.g., 367–473.33 MHz and 550–710 MHz ranges). These higher frequencies require operation in fractional synthesis mode and are subject to the constraint that no more than two unique frequencies above Fvco/8 may be simultaneously active. SI5334K-B04338-GMR maintains 0 ppm accuracy and low jitter across all supported bands, verified per JEDEC JESD65 cycle-cycle jitter measurements.

How is the SI5334K-B04338-GMR configured - via pins or serial interface?

The SI5334K-B04338-GMR is a pin-controlled device with factory-programmed non-volatile memory (OTP), meaning its configuration - including output frequencies, formats, voltage levels, and spread spectrum settings - is permanently stored during manufacturing and requires no external programming at power-up. Configuration is selected using hardware pins (e.g., REFCLKSE, FDBKSE, SSPB) at boot; there is no I²C, SPI, or other serial interface. SI5334K-B04338-GMR begins generating valid clocks within 2 ms of POR, enabling truly plug-and-play timing without host processor involvement.

What thermal and reliability specifications apply to the SI5334K-B04338-GMR?

The SI5334K-B04338-GMR is rated for operation from –40 °C to +85 °C ambient temperature, with thermal resistance θJA = 37 °C/W (still air) and θJC = 25 °C/W. It complies with JEDEC JESD78 latch-up immunity and features HBM ESD tolerance of 2.5 kV. Absolute maximum ratings include VDD = –0.5 to 3.8 V and junction temperature ≤150 °C. SI5334K-B04338-GMR is qualified per industry standards for telecom and industrial applications, with guaranteed performance across voltage and temperature extremes as specified in Tables 1–3 of the official datasheet Rev. 1.3.

SI5334K-B04338-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334K-B04338-GMR FAQ

1.How can I place an order for SI5334K-B04338-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334K-B04338-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334K-B04338-GMR reliable?

The price and inventory of SI5334K-B04338-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334K-B04338-GMR is usually 5 days.

3.What payment methods are accepted for SI5334K-B04338-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334K-B04338-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334K-B04338-GMR?

SI5334K-B04338-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334K-B04338-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334K-B04338-GMR?

For technical support, including SI5334K-B04338-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334K-B04338-GMR requirements.

6.How does Aetrix verify that SI5334K-B04338-GMR is sourced from the original manufacturer or authorized distributors?

All SI5334K-B04338-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334K-B04338-GMR meets industry standards.

7.What is the process for return or replacement of SI5334K-B04338-GMR?

All SI5334K-B04338-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5334K-B04338-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334K-B04338-GMR part is unused and in its original packaging.

Return procedure for SI5334K-B04338-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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