Skyworks Solutions Inc. SI5334K-B04339-GM
- Part No.:
- SI5334K-B04339-GM
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5334K-B04339-GM.pdf
- Description:
- 4-OUTPUT, ANY FREQUENCY(<710MHZ)
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5334K-B04339-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, 350 MHz max integer-output frequency (up to 710 MHz at select frequencies), and factory-programmed configuration for immediate operation on power-up. It serves as a high-precision timing source in PCIe 3.0, Ethernet switch/router, and FPGA clocking systems.
For engineers reviewing the SI5334K-B043339-GM datasheet, SI5334K-B04339-GM pinout, SI5334K-B04339-GM application, or SI5334K-B04339-GM equivalent, key selection considerations include its MultiSynth-based zero-ppm synthesis per output, independent output voltage control (1.5/1.8/2.5/3.3 V), 4×4 mm 24-QFN package, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL signal formats across all four outputs.
Technical Context
The SI5334K-B04339-GM integrates a fractional-N PLL with integrated VCO and loop filter, plus four independent MultiSynth output dividers enabling non-integer frequency synthesis on each of the four differential outputs. Its input stage accepts 8–30 MHz crystals or 5–710 MHz differential/single-ended clocks, with R-divider options for reference scaling.
Each output driver supports independent format selection (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL) and independent output supply voltage (VDDOx = 1.4–3.63 V), while core supply operates at 1.8/2.5/3.3 V. The device implements pin-controlled phase adjustment (<20 ps step, ±45 ns range) and frequency increment/decrement (1 ppm steps, glitchless, up to 350 MHz range) on CLK0A/B only.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Count & Type | 4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B), each independently configurable |
| Frequency Range | 0.16–350 MHz (integer mode), up to 710 MHz (select frequencies); supports any-frequency synthesis via MultiSynth |
| Phase Jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), meeting PCIe 3.0 and GbE jitter requirements |
| Frequency Accuracy | True 0 ppm error on all outputs - no calibration required, guaranteed by fractional-N synthesis |
| Supply Voltages | Core: 1.8/2.5/3.3 V; Output buffers: independently selectable 1.5/1.8/2.5/3.3 V per driver |
| Package | 24-pin QFN, 4 × 4 mm, 0.5 mm pitch - space-efficient for dense timing subsystems |
| Operating Temp | –40 °C to +85 °C ambient - qualified for industrial and telecom line card environments |
Pinout & Package
SI5334K-B04339-GM is housed in a 24-lead, 4 × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5334 family layout and match the standard Si5334 pinout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1 / IN2 | Differential reference input (primary) | Accepts 5–710 MHz AC-coupled differential clock; internal 10 kΩ termination enables direct connection to LVDS/HCSL sources |
| IN3 / IN4 | Single-ended reference input | Supports CMOS/SSTL/HSTL inputs from 5–350 MHz; VIH/VIL thresholds scale with VDD |
| CLK0A / CLK0B | Differential output 0 | Primary output supporting pin-controlled frequency increment/decrement (1 ppm steps, glitchless) |
| CLK1A / CLK1B | Differential output 1 | Fully programmable output; supports same format/frequency flexibility as CLK0, but no pin-controlled freq adjust |
| CLK2A / CLK2B | Differential output 2 | Independent output with full MultiSynth synthesis; usable for secondary system clocks (e.g., SerDes reference) |
| CLK3A / CLK3B | Differential output 3 | Fourth independent output; supports identical format/voltage/frequency configuration as other outputs |
| VDDO0–VDDO3 | Output buffer supplies | Four dedicated pins allow independent voltage setting per output driver (1.5/1.8/2.5/3.3 V) |
| VDD | Core supply | Supplies internal PLL, logic, and memory; accepts 1.8/2.5/3.3 V with ±10% tolerance |
| OEB | Output enable (active-low) | Hardware-controlled global disable of all outputs; useful for power sequencing and test modes |
| LOSLOL | Loss-of-signal/loss-of-lock alarm | Open-drain output asserting low on input clock loss or PLL unlock; enables system-level fault monitoring |
| RSVD_GND | Reserved ground | Internally connected to die substrate; must be tied to PCB ground plane for EMI and thermal performance |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth frequency synthesis | Enables independent, any-frequency generation on all four outputs with zero ppm error - eliminates need for multiple crystals or external synthesizers |
| Pin-controlled frequency adjust | Glitchless 1 ppm-step frequency increment/decrement on CLK0A/B only - supports margin testing and dynamic clock tuning without I²C or firmware |
| Per-output voltage and format control | Each output supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL with independent VDDO supply - simplifies mixed-voltage board design |
| PCIe 2.0-compliant spread spectrum | SSC available on any 100 MHz output with 0.5% deviation at 30–33 kHz - reduces EMI without requiring host controller coordination |
| Factory-programmed OTP configuration | Device powers up and delivers configured clocks immediately - no boot-time initialization or external programming required |
Applications
| PCI Express 3.0 Timing | Ethernet Switch Clocking |
|---|---|
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe 3.0 endpoints and root complexes in a high-density switch fabric. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz clocks with matched phase alignment and SSC capability. Use Value: Meets PCIe 3.0 total jitter limit (<33.6 ps pk-pk) and enables EMI reduction via built-in spread spectrum on designated outputs. |
Use Scenario: Generating 125 MHz, 156.25 MHz, and 250 MHz clocks for 1/10 GbE PHYs, MACs, and packet processors in enterprise switches. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single crystal input. Use Value: Eliminates need for multiple oscillators or clock trees; 0.7 ps RMS jitter ensures clean sampling margins for high-speed SerDes interfaces. |
| FPGA & Processor Clocking | Broadcast Video Timing |
Use Scenario: Supplying multiple asynchronous clocks (e.g., 100 MHz AXI, 200 MHz DDR, 300 MHz video engine) to Xilinx/Intel FPGAs and SoCs. IC Role / Device Role / Timing Role: Configurable quad clock source with independent output voltage and format per domain (LVDS for DDR, HCSL for PCIe, CMOS for logic). Use Value: Reduces BOM count and PCB area vs. discrete clock ICs; per-output VDDO enables direct interface to mixed-supply FPGA banks. |
Use Scenario: Delivering SMPTE ST 2082 (12G-SDI) 297 MHz, ST 2081 (6G-SDI) 148.5 MHz, and ST 292 (HD-SDI) 74.25 MHz clocks in broadcast camera and routing equipment. IC Role / Device Role / Timing Role: High-stability, low-phase-noise clock generator supporting exact broadcast-standard frequencies with <10 ps cycle-cycle jitter. Use Value: Ensures bit-error-free transmission over long coaxial runs; phase adjustment feature allows fine skew compensation between video/audio paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332B-D06989-GM | Higher integration: includes integrated crystal, smaller 3 × 3 mm 24-QFN, supports up to 10 outputs (via fanout), lower typical jitter (0.5 ps RMS) | Targeted at space-constrained designs needing higher channel count or crystal-less operation; not pin-compatible | Select when board space is critical or >4 outputs needed; requires revalidation of layout and power delivery due to different pinout and thermal profile |
| ICS8430I-01T | Fixed-frequency (non-synthesizing) quad LVDS clock generator; 0.8 ps RMS jitter; no frequency/phase adjust; 3.3 V only; 32-TQFP package | Suitable only for static clock trees where frequencies are known and unchanging; lacks any-frequency synthesis or voltage flexibility | Choose only if all required frequencies are fixed and match ICS8430I-01T's preprogrammed outputs; avoid when dynamic tuning or mixed-voltage interfacing is needed |
Compared with SI5334K-B04339-GM, Si5332B-D06989-GM offers superior integration and jitter but demands layout redesign, while ICS8430I-01T provides simpler implementation for static clock distribution but sacrifices synthesis flexibility, voltage scalability, and phase control - making SI5334K-B04339-GM optimal for adaptable, multi-standard timing in programmable systems.
Availability
SI5334K-B04339-GM is available at Aetrix Electronics and suitable for PCIe 3.0 timing, Ethernet switch/router clocking, and FPGA/processor clocking applications requiring stable component supply, long-term lifecycle support, and guaranteed factory programming.
Supply support for SI5334K-B04339-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure, automotive, and industrial markets.
The Si5334 product line delivers pin-configurable, any-frequency clock generation for high-speed digital systems - designed specifically to replace multiple fixed-frequency oscillators and simplify timing architecture in PCIe, Ethernet, and FPGA-based platforms.
FAQ
What is the maximum output frequency supported by the SI5334K-B04339-GM?
The SI5334K-B04339-GM supports up to 350 MHz in integer synthesis mode on all four outputs. For select frequencies, it achieves up to 710 MHz using fractional-N MultiSynth - confirmed in Skyworks' datasheet Section 1, Table 4, and functional description. This capability applies to all outputs, though specific high-frequency configurations require proper VCO and divider settings.
Does the SI5334K-B04339-GM require I²C programming to operate?
No. The SI5334K-B04339-GM is factory-programmed with one-time programmable (OTP) memory and powers up immediately delivering its configured outputs without I²C, SPI, or firmware intervention. Pin control (e.g., OEB, frequency adjust pins) enables runtime adjustments, but basic operation is autonomous - as stated in the "Description" and "Power-Up" sections of the datasheet.
Can the SI5334K-B04339-GM generate both differential and single-ended outputs simultaneously?
Yes. The SI5334K-B04339-GM supports up to four differential outputs (LVPECL/LVDS/HCSL) or eight single-ended outputs (CMOS/SSTL/HSTL), or any combination - e.g., two LVDS pairs and two CMOS clocks. Each output driver is independently configurable per Skyworks' "Output Driver" section (page 16) and Table 4, with appropriate termination and load conditions applied per format.
What is the purpose of the LOSLOL pin on the SI5334K-B04339-GM?
The LOSLOL pin on the SI5334K-B04339-GM is an open-drain alarm output that asserts low during loss-of-signal (on reference input) or loss-of-lock (PLL unlock). Its deassertion time is 0.01–1 µs and assertion time is 2.6–5 µs, enabling real-time system fault detection without polling. It connects directly to FPGA GPIO or supervisor ICs for fail-safe timing monitoring.
Is spread spectrum clocking (SSC) supported on all outputs of the SI5334K-B04339-GM?
Spread spectrum clocking is supported on any SI5334K-B04339-GM output clock operating at exactly 100 MHz and configured with Rn divider = 1 - per datasheet Section 2.10 and Table 3 note 4. It is PCI Express 2.0 compliant (–0.5% deviation, 30–33 kHz modulation rate) but not available at other frequencies or divider settings.
SI5334K-B04339-GM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5334K-B04339-GM FAQ
1.How can I place an order for SI5334K-B04339-GM through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5334K-B04339-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5334K-B04339-GM reliable?
The price and inventory of SI5334K-B04339-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334K-B04339-GM is usually 5 days.
3.What payment methods are accepted for SI5334K-B04339-GM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334K-B04339-GM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5334K-B04339-GM?
SI5334K-B04339-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5334K-B04339-GM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5334K-B04339-GM?
For technical support, including SI5334K-B04339-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334K-B04339-GM requirements.
6.How does Aetrix verify that SI5334K-B04339-GM is sourced from the original manufacturer or authorized distributors?
All SI5334K-B04339-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334K-B04339-GM meets industry standards.
7.What is the process for return or replacement of SI5334K-B04339-GM?
All SI5334K-B04339-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334K-B04339-GM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5334K-B04339-GM part is unused and in its original packaging.
Return procedure for SI5334K-B04339-GM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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