Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334K-B04796-GM

Name: SI5334K-B04796-GM
Brand: Skyworks Solutions Inc.
SKU: SI5334K-B04796-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5334K-B04796-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334K-B04796-GM.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<710MHZ)

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,371

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5334K-B04796-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs, 0.7 ps RMS typical phase jitter, 0 ppm frequency accuracy, and support for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats up to 710 MHz - deployed in Ethernet switch/router and PCI Express 3.0 timing systems.

For engineers reviewing the SI5334K-B04796-GM datasheet, SI5334K-B04796-GM pinout, SI5334K-B04796-GM application, or SI5334K-B04796-GM equivalent, key selection considerations include its 24-pin QFN package, factory-programmed configuration, 1.8/2.5/3.3 V core supply compatibility, independent output voltage per driver (1.5–3.3 V), and PCIe 2.0-compliant spread spectrum on 100 MHz outputs.

Technical Context

The SI5334K-B04796-GM integrates a fractional-N PLL with patented MultiSynth synthesis stages - one per output - enabling independent non-integer frequency generation with zero ppm error. Each output supports programmable initial phase offset (±45 ns) and 20 ps step phase adjustment.

It accepts multiple reference inputs: 8–30 MHz crystal, 5–200 MHz CMOS, 5–350 MHz SSTL/HSTL, or 5–710 MHz differential clock. The device operates across –40 to +85 °C and supports optional zero-delay mode via external feedback on FDBK/FDBKB pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B), each independently configurable
Frequency range	0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS with specific divider configurations
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting stringent GbE and PCIe 3.0 timing requirements
Core supply voltage	1.8 V, 2.5 V, or 3.3 V - selectable per design; supports mixed-voltage system integration
Output voltage per driver	Independent VDDOx (1.5 V, 1.8 V, 2.5 V, or 3.3 V) enables mixed-signal interface without level shifters
Spread spectrum	PCIe 2.0-compliant on any 100 MHz output; reduces EMI without affecting system timing margin
Package	24-pin QFN, 4 mm × 4 mm - space-constrained PCBs with thermal resistance θJA = 37 °C/W

Pinout & Package

SI5334K-B04796-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Rev. 1.3 datasheet (page 23), supporting pin-strapped configuration without I²C interface.

Pin/Terminal	Circuit Role	Design Meaning
IN1/IN2, IN5/IN6	Differential reference input	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3/IN4	Single-ended reference input	Supports 5–200 MHz CMOS-level clock; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A/CLK0B to CLK3A/CLK3B	Differential clock outputs	Four independent pairs; each configurable for LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL
VDDO0–VDDO3	Output buffer supplies	Independent 1.5–3.3 V per output pair - enables mixed-voltage signaling on same device
VDD	Core supply	1.8/2.5/3.3 V ±10%; IDD = 45 mA typical at 100 MHz on all outputs
LOSLOL	Loss-of-signal/loss-of-lock alarm	Open-drain output; asserts low within 5 µs on input loss or PLL unlock
OEB	Output enable/disable	Active-low control; disables all outputs simultaneously without reconfiguration
RSVD_GND	Reserved ground	Internally connected to substrate; must be tied to PCB ground plane

Key Features

Feature	Design Value
MultiSynth frequency synthesis	Four independent fractional-N synthesis paths deliver true 0 ppm frequency accuracy on all outputs
Glitchless frequency increment/decrement	1 ppm steps on CLK0A/B only; enables real-time frequency margining during test or runtime adaptation
Programmable phase offset	±45 ns range with <20 ps resolution per output - critical for skew-sensitive SerDes alignment
Zero-delay mode	External feedback via FDBK/FDBKB pins eliminates static phase offset between reference and selected output
Pin-controlled operation	No I²C bus required; configuration set at power-up from OTP memory - simplifies firmware and reduces BOM

Applications

Ethernet Switch/Router Timing	PCI Express 3.0 Clocking
Use Scenario: Synchronizing multi-lane 10 GbE PHYs and packet switching fabric in carrier-grade switches. IC Role / Device Role / Timing Role: Primary clock generator providing four low-jitter, independently timed clocks for MAC, PHY, CPU, and management subsystems. Use Value: 0.7 ps RMS jitter ensures compliance with IEEE 802.3ae jitter budgets; independent output voltage control matches diverse ASIC I/O standards.	Use Scenario: Delivering synchronized 100 MHz reference clocks to PCIe root complex and endpoint devices in server motherboards. IC Role / Device Role / Timing Role: Quad-output PCIe-compliant clock source with spread spectrum enabled on dedicated 100 MHz outputs. Use Value: PCIe 2.0-compliant SSC reduces EMI without violating PCIe 3.0 total jitter limits (<0.45 ps RMS); pin-strapped operation eliminates firmware dependency.
Broadcast Video Timing	FPGA Processor Clocking
Use Scenario: Generating genlock-capable pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio sample clocks (48 kHz, 96 kHz) in SDI video encoders. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact SMPTE-standard frequencies from a single crystal reference. Use Value: MultiSynth architecture achieves zero ppm error on all outputs - eliminating frame sync drift in multi-channel broadcast infrastructure.	Use Scenario: Supplying differentiated clocks to FPGA fabric (e.g., 300 MHz), transceivers (e.g., 125 MHz), DDR controller (e.g., 400 MHz), and peripherals (e.g., 50 MHz). IC Role / Device Role / Timing Role: Configurable quad clock generator enabling optimal clock domain partitioning without external dividers. Use Value: Independent output format and voltage per channel eliminate level-shifting components; 24-QFN footprint saves board area versus discrete solutions.

Ethernet Switch/Router Timing

PCI Express 3.0 Clocking

Use Scenario: Synchronizing multi-lane 10 GbE PHYs and packet switching fabric in carrier-grade switches.

IC Role / Device Role / Timing Role: Primary clock generator providing four low-jitter, independently timed clocks for MAC, PHY, CPU, and management subsystems.

Use Value: 0.7 ps RMS jitter ensures compliance with IEEE 802.3ae jitter budgets; independent output voltage control matches diverse ASIC I/O standards.

Use Scenario: Delivering synchronized 100 MHz reference clocks to PCIe root complex and endpoint devices in server motherboards.

IC Role / Device Role / Timing Role: Quad-output PCIe-compliant clock source with spread spectrum enabled on dedicated 100 MHz outputs.

Use Value: PCIe 2.0-compliant SSC reduces EMI without violating PCIe 3.0 total jitter limits (<0.45 ps RMS); pin-strapped operation eliminates firmware dependency.

Broadcast Video Timing

FPGA Processor Clocking

Use Scenario: Generating genlock-capable pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and audio sample clocks (48 kHz, 96 kHz) in SDI video encoders.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact SMPTE-standard frequencies from a single crystal reference.

Use Value: MultiSynth architecture achieves zero ppm error on all outputs - eliminating frame sync drift in multi-channel broadcast infrastructure.

Use Scenario: Supplying differentiated clocks to FPGA fabric (e.g., 300 MHz), transceivers (e.g., 125 MHz), DDR controller (e.g., 400 MHz), and peripherals (e.g., 50 MHz).

IC Role / Device Role / Timing Role: Configurable quad clock generator enabling optimal clock domain partitioning without external dividers.

Use Value: Independent output format and voltage per channel eliminate level-shifting components; 24-QFN footprint saves board area versus discrete solutions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06889-GM	Higher integration: 8 outputs, integrated EEPROM, I²C programmability; 0.5 ps RMS jitter; supports JESD204B deterministic latency	Required for JESD204B-compliant data converters or systems needing dynamic reconfiguration	Select when field programmability, higher channel count, or sub-0.5 ps jitter is mandatory - not pin-compatible
ICS843002AGI-01LFT	Fixed-frequency quad LVDS generator (100/125/156.25 MHz); no frequency synthesis; 1.2 ps RMS jitter; 32-pin QFN	Suitable only for static, standard-frequency applications like Gigabit Ethernet PHY clocks	Choose for cost-sensitive, non-synthesizing use cases where flexibility is unnecessary and lower jitter tolerance exists

Compared with Si5332A-D06889-GM, SI5334K-B04796-GM offers simpler pin-control deployment and lower system-level firmware overhead; compared with ICS843002AGI-01LFT, it delivers full any-frequency synthesis and superior jitter performance at the cost of greater configuration complexity.

Availability

SI5334K-B04796-GM is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCI Express 3.0 clocking, and broadcast video synchronization requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for SI5334K-B04796-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si5334 family is designed as a high-flexibility, low-jitter clock generator platform targeting multi-protocol timing in networking, computing, and broadcast infrastructure - emphasizing pin-strapped simplicity and factory-programmed reliability.

FAQ

What is the primary function of the SI5334K-B04796-GM in a timing architecture?

The SI5334K-B04796-GM serves as a pin-controlled, any-frequency quad clock generator that synthesizes four independent, low-jitter differential clock outputs - each configurable from 0.16 MHz up to 710 MHz - using Skyworks' MultiSynth technology. It replaces multiple fixed-frequency oscillators and dividers, reducing bill-of-materials and layout complexity while ensuring 0 ppm frequency accuracy and 0.7 ps RMS phase jitter for demanding applications like PCIe 3.0 and 10 GbE.

Does the SI5334K-B04796-GM require an I²C interface for configuration?

No, the SI5334K-B04796-GM does not require an I²C interface. Its configuration is factory-programmed into one-time-programmable (OTP) memory and loaded automatically at power-up. All functional settings - including output frequencies, formats, voltages, and spread spectrum - are controlled via hardware pin strapping (e.g., OEB, LOSLOL, and reference input selection), eliminating firmware dependencies and simplifying system integration.

What reference inputs does the SI5334K-B04796-GM support?

The SI5334K-B04796-GM supports multiple reference sources: an 8–30 MHz fundamental-mode crystal connected to IN1/IN2, or external clock signals including 5–200 MHz CMOS (IN3/IN4), 5–350 MHz SSTL/HSTL, and 5–710 MHz differential (IN1/IN2 or IN5/IN6). Input flexibility allows seamless integration across legacy and high-speed designs without external signal conditioning.

Can the SI5334K-B04796-GM generate spread spectrum clocking for EMI reduction?

Yes, the SI5334K-B04796-GM supports PCIe 2.0-compliant spread spectrum clocking (SSC) on any output clock operating at exactly 100 MHz - provided the Rn divider is set to 1. SSC provides –0.5% frequency deviation at 30–33 kHz modulation rate, reducing electromagnetic interference without compromising timing integrity in host systems compliant with PCIe specifications.

How is output voltage configured on the SI5334K-B04796-GM?

Each of the four differential output pairs (CLK0 through CLK3) has its own dedicated output buffer supply pin (VDDO0–VDDO3), allowing independent selection of 1.5 V, 1.8 V, 2.5 V, or 3.3 V per channel. This enables direct interfacing with mixed-voltage ASICs, FPGAs, and PHYs - for example, driving a 1.8 V FPGA transceiver bank and a 3.3 V legacy controller simultaneously - without external level shifters or voltage translators.

SI5334K-B04796-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334K-B04796-GM FAQ

1.How can I place an order for SI5334K-B04796-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334K-B04796-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334K-B04796-GM reliable?

The price and inventory of SI5334K-B04796-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334K-B04796-GM is usually 5 days.

3.What payment methods are accepted for SI5334K-B04796-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334K-B04796-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334K-B04796-GM?

SI5334K-B04796-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334K-B04796-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334K-B04796-GM?

For technical support, including SI5334K-B04796-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334K-B04796-GM requirements.

6.How does Aetrix verify that SI5334K-B04796-GM is sourced from the original manufacturer or authorized distributors?

All SI5334K-B04796-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334K-B04796-GM meets industry standards.

7.What is the process for return or replacement of SI5334K-B04796-GM?

All SI5334K-B04796-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334K-B04796-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334K-B04796-GM part is unused and in its original packaging.

Return procedure for SI5334K-B04796-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…