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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334K-B05547-GM

Name: SI5334K-B05547-GM
Brand: Skyworks Solutions Inc.
SKU: SI5334K-B05547-GM
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334K-B05547-GM

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334K-B05547-GM.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<710MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334K-B05547-GM from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator IC with four independently configurable differential clock outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz per output using MultiSynth fractional-N synthesis, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, and operates from 1.8/2.5/3.3 V core and output supply rails. It is deployed in PCIe 3.0 timing, 10 GbE switch clocking, and FPGA reference clock distribution.

For engineers reviewing the SI5334K-B05547-GM datasheet, SI5334K-B05547-GM pinout, SI5334K-B05547-GM application, or SI5334K-B05547-GM equivalent, this device enables glitchless frequency tuning in 1 ppm steps, sub-20 ps phase adjustment per output, zero-delay mode via external feedback, loss-of-lock/loss-of-signal monitoring, and factory-programmed configuration requiring no runtime initialization.

Technical Context

The SI5334K-B05547-GM integrates a fully on-chip fractional-N PLL (phase detector, charge pump, loop filter, VCO, R/N dividers) and four independent MultiSynth output synthesis stages. Each MultiSynth supports integer or fractional division to generate any output frequency up to 350 MHz (or select frequencies to 710 MHz), with zero ppm frequency error and <20 ps phase step resolution.

Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. Output drivers are individually configurable for format (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), voltage (1.5/1.8/2.5/3.3 V), and termination - enabling mixed-voltage system clocking without level shifters.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs, each independently configurable - supports simultaneous mixed-format/mixed-frequency clock trees
Frequency range per output	0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS - covers PCIe Gen3 (100 MHz), 10GbE (156.25 MHz), and broadcast video (270 MHz)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz) - meets PCI Express 3.0 common clock jitter spec (<0.45 ps RMS)
Core supply voltage	1.8 V / 2.5 V / 3.3 V ±10% - enables direct interface with low-voltage FPGAs and processors without LDOs
Output supply per driver	1.5 V / 1.8 V / 2.5 V / 3.3 V - allows concurrent generation of 1.8 V LVDS and 3.3 V CMOS clocks on same device
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch - space-constrained board designs with thermal resistance θ_JA = 37 °C/W
Operating temperature	–40 °C to +85 °C - qualified for industrial and telecom line card environments

Pinout & Package

SI5334K-B05547-GM is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments follow the standard Si5334 pinout: IN1/IN2 (diff ref A), IN3/IN4 (SE ref), IN5/IN6 (diff ref B), CLK0A/CLK0B through CLK3A/CLK3B (four diff outputs), VDD (core supply), VDDO0–VDDO3 (per-output supplies), LOSLOL (alarm), OEB (output enable), and RSVD_GND.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input A	Accepts 5–710 MHz AC-coupled differential clock; requires external 100 Ω termination
IN3 / IN4	Single-ended reference input	Supports 5–200 MHz CMOS-level clock; VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A / CLK0B – CLK3A / CLK3B	Differential clock outputs (4 pairs)	Each pair independently configurable for LVPECL/LVDS/HCSL; output swing and common-mode voltage set by VDDOx
VDD	Core supply input	1.8/2.5/3.3 V ±10%; powers PLL, logic, and MultiSynth blocks
VDDO0 – VDDO3	Output buffer supply inputs	Independent 1.5/1.8/2.5/3.3 V rails per output pair - enables mixed-voltage clock distribution
LOSLOL	Loss-of-signal/loss-of-lock alarm output	Open-drain active-low signal asserting within 5 µs of input failure or PLL unlock
OEB	Output enable control	Active-low pin disabling all clock outputs simultaneously; used for power sequencing or system reset coordination

Key Features

Feature	Design Value
MultiSynth fractional-N synthesis	Enables any-frequency output generation (0.16–710 MHz) with zero ppm error - eliminates need for multiple fixed-frequency oscillators
Per-output voltage and format control	Each of four outputs supports independent selection of LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL and 1.5–3.3 V supply - removes external level translators in heterogeneous systems
Glitchless frequency increment/decrement	Adjusts CLK0A/B frequency in 1 ppm steps up to 350 MHz without output interruption - supports margin testing and dynamic clock scaling
Sub-20 ps phase adjustment	Programmable initial phase offset and real-time phase increment/decrement (±45 ns range, 20 ps resolution) - enables precise skew alignment across multi-lane SerDes
PCIe 2.0-compliant spread spectrum	Configurable SSC on any 100 MHz output (±0.5% deviation at 30–33 kHz) - reduces EMI without violating PCIe jitter compliance
Zero-delay mode	External feedback path from CLKn to FDBK/FDBKB pins nullifies reference-to-output phase delay - critical for deterministic latency in timing-critical loops

Applications

PCI Express 3.0 Clocking	Ethernet Switch Timing
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen3 endpoints and root complexes in a high-density switch ASIC. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz clocks with matched phase and SSC capability. Use Value: Meets PCIe 3.0 common clock jitter spec (≤0.45 ps RMS), eliminates inter-lane skew, and enables EMI reduction via spread spectrum on all four lanes.	Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs in a modular line card. IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single crystal reference. Use Value: Avoids discrete oscillator inventory; supports multi-rate operation with zero ppm error and <10 ps cycle-cycle jitter.
FPGA Reference Clock Distribution	Broadcast Video Synchronization
Use Scenario: Supplying clean, phase-aligned clocks to multiple high-speed transceivers, memory interfaces, and processing cores in Xilinx Versal or Intel Agilex FPGAs. IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output to match diverse FPGA I/O standards. Use Value: Eliminates need for separate LVDS, HCSL, and CMOS clock buffers; simplifies PCB layout with single 4×4 mm footprint.	Use Scenario: Delivering SMPTE ST 2082 (270 MHz), ST 292 (148.5 MHz), and ST 259 (27 MHz) reference clocks to video encoders, decoders, and routers in broadcast infrastructure. IC Role / Device Role / Timing Role: High-stability clock generator supporting exact video line rates with ultra-low jitter to prevent pixel errors and frame jitter. Use Value: 0.7 ps RMS jitter ensures bit-error-free transmission over SDI links; factory-programmed configuration guarantees repeatability across production units.

PCI Express 3.0 Clocking

Ethernet Switch Timing

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen3 endpoints and root complexes in a high-density switch ASIC.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter 100 MHz clocks with matched phase and SSC capability.

Use Value: Meets PCIe 3.0 common clock jitter spec (≤0.45 ps RMS), eliminates inter-lane skew, and enables EMI reduction via spread spectrum on all four lanes.

Use Scenario: Generating 125 MHz, 156.25 MHz, and 312.5 MHz clocks for 1/10/25 GbE PHYs and MACs in a modular line card.

IC Role / Device Role / Timing Role: Any-frequency synthesizer producing exact IEEE 802.3-compliant rates from a single crystal reference.

Use Value: Avoids discrete oscillator inventory; supports multi-rate operation with zero ppm error and <10 ps cycle-cycle jitter.

FPGA Reference Clock Distribution

Broadcast Video Synchronization

Use Scenario: Supplying clean, phase-aligned clocks to multiple high-speed transceivers, memory interfaces, and processing cores in Xilinx Versal or Intel Agilex FPGAs.

IC Role / Device Role / Timing Role: Configurable quad clock source with independent voltage and format per output to match diverse FPGA I/O standards.

Use Value: Eliminates need for separate LVDS, HCSL, and CMOS clock buffers; simplifies PCB layout with single 4×4 mm footprint.

Use Scenario: Delivering SMPTE ST 2082 (270 MHz), ST 292 (148.5 MHz), and ST 259 (27 MHz) reference clocks to video encoders, decoders, and routers in broadcast infrastructure.

IC Role / Device Role / Timing Role: High-stability clock generator supporting exact video line rates with ultra-low jitter to prevent pixel errors and frame jitter.

Use Value: 0.7 ps RMS jitter ensures bit-error-free transmission over SDI links; factory-programmed configuration guarantees repeatability across production units.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D05547-GM	Higher integration: integrated EEPROM, I²C programmability, and enhanced jitter performance (0.5 ps RMS); supports up to 12 outputs via fanout	Requires firmware initialization; better suited for dynamically reconfigured systems vs. fixed-function pin-control	Select when field reconfiguration, tighter jitter budgets, or >4 outputs are required - not drop-in compatible due to different pinout and control scheme
ICS8430I-01T	Fixed-frequency quad LVDS generator (100/125/156.25/200 MHz); no fractional synthesis; 1.2 ps RMS jitter; 3.3 V only	Limited to predefined frequencies; no phase/frequency tuning; no spread spectrum or zero-delay mode	Select only for cost-sensitive, static-clocking applications where frequency flexibility and advanced features are unnecessary

Compared with Si5332A-D05547-GM, SI5334K-B05547-GM offers simpler pin-control deployment and lower BOM count but lacks field programmability; compared with ICS8430I-01T, it provides full frequency agility and jitter performance headroom at higher complexity and cost.

Availability

SI5334K-B05547-GM is available at Aetrix Electronics and suitable for PCIe 3.0 timing, 10 GbE switch clocking, and FPGA reference clock distribution requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for SI5334K-B05547-GM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.

The Si5334 product line delivers pin-configurable, low-jitter clock generators for high-speed digital systems - designed specifically for applications demanding frequency flexibility, phase coherence, and robust jitter performance in networking, computing, and broadcast infrastructure.

FAQ

What is the maximum output frequency supported by SI5334K-B05547-GM?

The SI5334K-B05547-GM supports up to 710 MHz on LVPECL and LVDS outputs, and up to 350 MHz on all other formats including HCSL, CMOS, SSTL, and HSTL. This capability enables direct generation of PCIe Gen3 (100 MHz), 10GbE (156.25 MHz), and broadcast video (270 MHz) clocks without external multiplication. The 710 MHz limit applies only when using LVPECL/LVDS with appropriate VDDO and load conditions.

Does SI5334K-B05547-GM require an external configuration EEPROM or I²C interface?

No, SI5334K-B05547-GM does not require external memory or I²C communication. Its configuration is factory-programmed into one-time-programmable (OTP) NVM. Upon power-up, the device begins operation immediately in the predefined state - no host processor or initialization sequence is needed. Pin control (e.g., OEB, LOSLOL) provides runtime management without software overhead.

Can SI5334K-B05547-GM generate spread spectrum clocking (SSC) for EMI reduction?

Yes, SI5334K-B05547-GM supports PCI Express 2.0-compliant spread spectrum on any output clock operating at exactly 100 MHz. The modulation depth is ±0.5% at a rate of 30–33 kHz. SSC is enabled per-output via factory programming and does not require pin control or runtime commands - making it suitable for fixed EMI mitigation in storage and server applications.

What input reference sources are compatible with SI5334K-B05547-GM?

SI5334K-B05547-GM accepts multiple reference types: an 8–30 MHz fundamental-mode crystal directly connected to IN1/IN2; a single-ended CMOS clock (5–200 MHz) on IN3 or IN4; or differential clock inputs (5–710 MHz) on IN1/IN2 or IN5/IN6. Input voltage thresholds are rail-relative (VIH = 0.7×VDD), and slew rate requirements (≥1 V/ns for SE, ≥0.3 V/ns for diff) must be met to maintain specified jitter performance.

How is phase alignment controlled across the four outputs of SI5334K-B05547-GM?

SI5334K-B05547-GM provides per-output programmable initial phase offset (–45 to +45 ns) and real-time phase increment/decrement with <20 ps resolution. These adjustments are pin-controlled and operate at up to 1.5 MHz update rate. Phase tuning is available across the full 0.16–350 MHz output range, enabling precise skew matching between SerDes lanes, memory channels, or multi-die packages without external delay lines.

SI5334K-B05547-GM Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334K-B05547-GM FAQ

1.How can I place an order for SI5334K-B05547-GM through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334K-B05547-GM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334K-B05547-GM reliable?

The price and inventory of SI5334K-B05547-GM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334K-B05547-GM is usually 5 days.

3.What payment methods are accepted for SI5334K-B05547-GM?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334K-B05547-GM transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334K-B05547-GM?

SI5334K-B05547-GM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334K-B05547-GM order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334K-B05547-GM?

For technical support, including SI5334K-B05547-GM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334K-B05547-GM requirements.

6.How does Aetrix verify that SI5334K-B05547-GM is sourced from the original manufacturer or authorized distributors?

All SI5334K-B05547-GM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334K-B05547-GM meets industry standards.

7.What is the process for return or replacement of SI5334K-B05547-GM?

All SI5334K-B05547-GM units undergo pre-shipment inspection (PSI). If there is an issue with SI5334K-B05547-GM, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334K-B05547-GM part is unused and in its original packaging.

Return procedure for SI5334K-B05547-GM:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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