Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334M-B04510-GMR

Name: SI5334M-B04510-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5334M-B04510-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SI5334M-B04510-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334M-B04510-GMR.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,546

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SI5334M-B04510-GMR from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs, 0.7 ps RMS typical phase jitter, 1.8/2.5/3.3 V core supply support, and operation up to 710 MHz on select outputs - deployed in Ethernet switch timing, PCIe 3.0 clocking, and FPGA reference distribution.

For engineers reviewing the SI5334M-B04510-GMR datasheet, SI5334M-B04510-GMR pinout, SI5334M-B04510-GMR application, or SI5334M-B04510-GMR equivalent, this page delivers verified specifications, factory-programmed configuration details, output format flexibility (LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL), and real-world jitter performance data per PCI Express 3.0 and GbE standards.

Technical Context

The SI5334M-B04510-GMR integrates a fractional-N PLL with patented MultiSynth synthesis engines - one per output - enabling independent integer or fractional frequency generation from a single crystal (8–30 MHz) or wideband differential input (5–710 MHz). Each output supports programmable initial phase offset (±45 ns) and 20 ps step phase adjustment.

It implements pin-controlled frequency increment/decrement (1 ppm steps, glitchless, up to 1.5 MHz update rate) on CLK0A/B only, and supports spread spectrum on 100 MHz outputs compliant with PCI Express 2.0. Loss-of-signal (LOS) and loss-of-lock (LOL) monitoring are provided via dedicated LOSLOL pin.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs (CLK0A/B, CLK1A/B, CLK2A/B, CLK3A/B), each independently configurable
Frequency range	0.16–350 MHz on all outputs; select frequencies up to 710 MHz (e.g., LVPECL/LVDS at 367–473.33 MHz and 550–710 MHz)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz), meeting PCIe 3.0 ≤0.45 ps RMS and GbE ≤1 ps RMS requirements
Core supply voltage	1.8 V (±5%), 2.5 V (±10%), or 3.3 V (±10%) - selectable per design; 45 mA typical core current at 100 MHz on all outputs
Output format support	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - each output has independent VDDO (1.5/1.8/2.5/3.3 V)
Input reference options	Crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz)
Package	24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch, exposed thermal pad

Pinout & Package

SI5334M-B04510-GMR is housed in a 24-lead QFN package (4 × 4 mm, 0.5 mm pitch) with exposed thermal pad for enhanced thermal performance. Pin assignments follow Skyworks' standard Si5334 top-view layout.

Pin/Terminal	Circuit Role	Design Meaning
IN1 / IN2	Differential reference input pair	Accepts AC-coupled differential clock (5–710 MHz); internal 10 kΩ termination; requires external 100 Ω load
IN3 / IN4	Single-ended reference input pair	Supports CMOS/SSTL/HSTL inputs (5–350 MHz); VIH = 0.7×VDD, VIL = 0.3×VDD
CLK0A / CLK0B	Differential output pair 0	Factory-configured primary output; supports frequency increment/decrement (1 ppm steps) and phase adjustment
CLK1A / CLK1B	Differential output pair 1	Fully independent synthesis path; supports same format/frequency flexibility as CLK0
CLK2A / CLK2B	Differential output pair 2	Independent MultiSynth engine; usable for secondary system clocks (e.g., PHY or SerDes reference)
CLK3A / CLK3B	Differential output pair 3	Fourth independent output; supports identical signal formats and voltage scaling (VDDO3)
VDD	Core supply	Connects to 1.8/2.5/3.3 V core rail; decoupling required per datasheet layout guidelines
VDDO0–VDDO3	Output buffer supplies	Independent per-output supply pins (1.5/1.8/2.5/3.3 V); enable mixed-voltage system interfacing
LOSLOL	Loss-of-signal/loss-of-lock alarm	Open-drain output asserting low on input failure or PLL unlock; 3 mA sink capability
OEB	Output enable bar	Active-low global output disable; synchronously gates all four differential output drivers
RSVD_GND	Reserved ground	Internally connected to die substrate; must be tied to PCB ground plane

Key Features

Feature	Design Value
MultiSynth synthesis per output	Enables independent, zero-ppm-error frequency generation on all four outputs - no shared dividers or frequency coupling
Pin-controlled frequency tuning	Glitchless 1 ppm step increments/decrements on CLK0A/B only - eliminates need for I²C interface in margining or dynamic frequency control
Programmable phase offset	±45 ns initial phase setting per output with 20 ps resolution - critical for skew-sensitive SerDes or DDR timing alignment
PCIe 2.0-compliant spread spectrum	Available on any 100 MHz output with Rn divider = 1; ±0.5% deviation at 30–33 kHz - reduces EMI without affecting timing margins
Flexible output voltage per driver	VDDO0–VDDO3 support 1.5/1.8/2.5/3.3 V - allows direct interfacing to mixed-supply FPGAs, ASICs, and PHYs without level shifters

Applications

Ethernet Switch Timing	PCI Express 3.0 Clocking
Use Scenario: Synchronizing multiple 10 GbE PHYs and packet processors in Layer 3 switches with sub-100 ps skew tolerance. IC Role / Device Role / Timing Role: Primary quad-output clock source delivering independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 25 MHz (management) clocks. Use Value: Eliminates need for multiple discrete oscillators; 0.7 ps RMS jitter ensures compliance with IEEE 802.3bj and PCIe 3.0 jitter budgets.	Use Scenario: Providing reference clocks to CPU, GPU, and peripheral controllers in high-performance computing platforms. IC Role / Device Role / Timing Role: Generating 100 MHz PCIe 3.0 common clock and 100 MHz spread-spectrum clock simultaneously on separate outputs. Use Value: Meets PCIe 3.0 total jitter <33.6 ps pk-pk and RMS jitter ≤0.45 ps; SSC on one output reduces EMI without compromising timing integrity on others.
FPGA Reference Distribution	Broadcast Video Timing
Use Scenario: Supplying multiple clock domains to Xilinx Versal or Intel Agilex FPGAs requiring LVDS, HCSL, and CMOS outputs concurrently. IC Role / Device Role / Timing Role: Delivering 300 MHz (HCSL for transceivers), 100 MHz (LVDS for logic), 50 MHz (CMOS for peripherals), and 27 MHz (SSTL for video interfaces). Use Value: Independent VDDO per output enables direct connection to mixed-voltage FPGA banks; eliminates external level translators and associated board area.	Use Scenario: Genlock-capable timing for SMPTE ST 2081 (12G-SDI) and ST 2110 (IP video) equipment requiring ultra-low-jitter 74.25 MHz and 148.5 MHz references. IC Role / Device Role / Timing Role: Synthesizing exact broadcast frequencies from a single 27 MHz crystal with zero ppm error and <10 ps cycle-cycle jitter. Use Value: Replaces TCXO + fanout buffer solutions; 0.7 ps RMS jitter meets SMPTE RP 184-2019 jitter mask for 12G-SDI.

Ethernet Switch Timing

PCI Express 3.0 Clocking

Use Scenario: Synchronizing multiple 10 GbE PHYs and packet processors in Layer 3 switches with sub-100 ps skew tolerance.

IC Role / Device Role / Timing Role: Primary quad-output clock source delivering independent 156.25 MHz (XAUI), 125 MHz (GbE), 100 MHz (PCIe), and 25 MHz (management) clocks.

Use Value: Eliminates need for multiple discrete oscillators; 0.7 ps RMS jitter ensures compliance with IEEE 802.3bj and PCIe 3.0 jitter budgets.

Use Scenario: Providing reference clocks to CPU, GPU, and peripheral controllers in high-performance computing platforms.

IC Role / Device Role / Timing Role: Generating 100 MHz PCIe 3.0 common clock and 100 MHz spread-spectrum clock simultaneously on separate outputs.

Use Value: Meets PCIe 3.0 total jitter <33.6 ps pk-pk and RMS jitter ≤0.45 ps; SSC on one output reduces EMI without compromising timing integrity on others.

FPGA Reference Distribution

Broadcast Video Timing

Use Scenario: Supplying multiple clock domains to Xilinx Versal or Intel Agilex FPGAs requiring LVDS, HCSL, and CMOS outputs concurrently.

IC Role / Device Role / Timing Role: Delivering 300 MHz (HCSL for transceivers), 100 MHz (LVDS for logic), 50 MHz (CMOS for peripherals), and 27 MHz (SSTL for video interfaces).

Use Value: Independent VDDO per output enables direct connection to mixed-voltage FPGA banks; eliminates external level translators and associated board area.

Use Scenario: Genlock-capable timing for SMPTE ST 2081 (12G-SDI) and ST 2110 (IP video) equipment requiring ultra-low-jitter 74.25 MHz and 148.5 MHz references.

IC Role / Device Role / Timing Role: Synthesizing exact broadcast frequencies from a single 27 MHz crystal with zero ppm error and <10 ps cycle-cycle jitter.

Use Value: Replaces TCXO + fanout buffer solutions; 0.7 ps RMS jitter meets SMPTE RP 184-2019 jitter mask for 12G-SDI.

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D08510-GM	8-output, higher integration (integrated LDOs, I²C + pin control), lower jitter (0.5 ps RMS), but larger 32-QFN package	Required for systems needing >4 outputs or tighter jitter specs (e.g., 5G baseband, optical line cards)	Select when scalability beyond 4 outputs or sub-0.6 ps jitter is mandatory; not drop-in due to pin count and footprint change
ICS8430I-01T	4-output, fixed-frequency (non-synthesizing), LVDS-only, 1.2 ps RMS jitter, 3.3 V only, no spread spectrum	Suitable for cost-sensitive, static-clock applications (e.g., legacy storage controllers) where frequency agility is unnecessary	Choose only if design uses fixed frequencies and avoids synthesizer complexity; incompatible with any-frequency or multi-voltage requirements of SI5334M-B04510-GMR

Compared with Si5332A-D08510-GM and ICS8430I-01T, SI5334M-B04510-GMR uniquely balances 4-output flexibility, pin-control simplicity, 0.7 ps RMS jitter, and multi-format/multi-voltage support in a compact 24-QFN - making it optimal for space-constrained, multi-protocol embedded systems requiring field-programmable timing.

Availability

SI5334M-B04510-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe 3.0 clocking, and broadcast video/audio timing requiring stable component supply across industrial temperature ranges (–40 to +85 °C).

Supply support for SI5334M-B04510-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog ICs for infrastructure, automotive, and industrial markets.

The Si5334 product line delivers pin-configurable, low-jitter clock generators for systems demanding flexible, high-fidelity timing - targeting networking, data center, and broadcast equipment where frequency agility and jitter performance are critical.

FAQ

What is the maximum output frequency supported by SI5334M-B04510-GMR?

The SI5334M-B04510-GMR supports up to 350 MHz on all four differential outputs under standard MultiSynth integer mode. For select frequencies, it delivers 367–473.33 MHz and 550–710 MHz - specifically with LVPECL or LVDS output formats. These higher frequencies require proper VCO calibration and are validated per Skyworks' frequency plan documentation for this variant.

Does SI5334M-B04510-GMR support spread spectrum clocking (SSC)?

Yes, SI5334M-B04510-GMR supports PCI Express 2.0-compliant spread spectrum on any output clock operating at exactly 100 MHz, provided the Rn divider is set to 1. The modulation is ±0.5% deviation at 30–33 kHz - implemented without external components and fully compatible with PCIe 2.0 EMI reduction requirements.

Can SI5334M-B04510-GMR generate different output formats simultaneously?

Yes, SI5334M-B04510-GMR supports simultaneous LVPECL, LVDS, HCSL, CMOS, SSTL, and HSTL outputs - one format per output pair (CLK0A/B through CLK3A/B). Each output has its own VDDO supply (1.5/1.8/2.5/3.3 V), enabling true mixed-signal interfacing to diverse logic families without external level-shifting circuitry.

What reference inputs does SI5334M-B04510-GMR accept?

SI5334M-B04510-GMR accepts an 8–30 MHz fundamental-mode crystal directly, or single-ended CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) clock inputs. Input pins IN1/IN2 and IN5/IN6 support differential signals; IN3/IN4 support single-ended. All inputs include internal termination and slew-rate optimization guidance.

Is SI5334M-B04510-GMR pin-compatible with other Si5334 variants?

Yes, all Si5334 variants - including SI5334M-B04510-GMR - share identical 24-QFN pinout, package dimensions, and thermal pad layout. Differences reside in factory-programmed configuration (frequency plan, output formats, voltage settings), not physical connectivity. PCB designs can accommodate multiple Si5334 variants without layout revision.

SI5334M-B04510-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334M-B04510-GMR FAQ

1.How can I place an order for SI5334M-B04510-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334M-B04510-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334M-B04510-GMR reliable?

The price and inventory of SI5334M-B04510-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334M-B04510-GMR is usually 5 days.

3.What payment methods are accepted for SI5334M-B04510-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334M-B04510-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334M-B04510-GMR?

SI5334M-B04510-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334M-B04510-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334M-B04510-GMR?

For technical support, including SI5334M-B04510-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334M-B04510-GMR requirements.

6.How does Aetrix verify that SI5334M-B04510-GMR is sourced from the original manufacturer or authorized distributors?

All SI5334M-B04510-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334M-B04510-GMR meets industry standards.

7.What is the process for return or replacement of SI5334M-B04510-GMR?

All SI5334M-B04510-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5334M-B04510-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334M-B04510-GMR part is unused and in its original packaging.

Return procedure for SI5334M-B04510-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…