Skyworks Solutions Inc. SI5334M-B06018-GMR
- Part No.:
- SI5334M-B06018-GMR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Application Specific Clock/Timing
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
SI5334M-B06018-GMR.pdf
- Description:
- 4-OUTPUT, ANY FREQUENCY(<200MHZ)
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SI5334M-B06018-GMR from Skyworks Solutions is a pin-controlled, quad-output any-frequency clock generator with four independently configurable differential clock outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz per output using MultiSynth fractional-N synthesis, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, and operates from 1.8/2.5/3.3 V core and output supply voltages. It is deployed in PCIe 3.0 timing, 10 GbE switch clocking, and FPGA reference distribution.
For engineers reviewing the SI5334M-B06018-GMR datasheet, SI5334M-B06018-GMR pinout, SI5334M-B06018-GMR application, or SI5334M-B06018-GMR equivalent, this page provides verified technical context, factory-programmed configuration details, jitter performance data at 125 MHz and 155.52 MHz, pin-level control logic for frequency/phase adjustment, and validated alternative options for multi-output clock synthesis in telecom and high-speed serial interfaces.
Technical Context
The SI5334M-B06018-GMR implements a two-stage synthesis architecture: a primary fractional-N PLL (phase detector, charge pump, loop filter, VCO) followed by four independent MultiSynth dividers - each capable of integer or fractional division to generate arbitrary output frequencies with zero ppm error. Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references.
Each of the four differential output pairs (CLK0A/B through CLK3A/B) features independent voltage rail selection (1.5/1.8/2.5/3.3 V), format programmability, and pin-controlled phase/frequency tuning: ±45 ns phase offset in 20 ps steps, and 1 ppm frequency increments on CLK0A/B only. Loss-of-signal (LOSLOL) and output enable (OEB) pins provide system-level monitoring and control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output count & type | 4 differential clock outputs (CLK0A/B to CLK3A/B); supports up to 8 single-ended clocks via internal driver reconfiguration |
| Frequency range per output | 0.16–350 MHz (all formats); up to 710 MHz for LVPECL/LVDS with specific divider configurations |
| Phase jitter (RMS) | 0.7 ps typical (12 kHz–20 MHz), measured at 125 MHz output with 25 MHz crystal input |
| Core supply voltage | 1.8 V, 2.5 V, or 3.3 V ±10%; supports mixed-voltage system integration without level shifters |
| Output supply voltage per bank | VDDO0–VDDO3 independently set to 1.5/1.8/2.5/3.3 V; enables direct interfacing with diverse I/O standards |
| Package | 24-pin QFN, 4 mm × 4 mm, 0.5 mm pitch; thermally enhanced with exposed pad for ≤37 °C/W θJA |
| Operating temperature | –40 °C to +85 °C ambient; qualified for industrial and telecom line card environments |
Pinout & Package
SI5334M-B06018-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with wettable flanks and an exposed thermal pad. Pin 1 is marked by a dot; the package is RoHS-compliant and lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN1/IN2, IN5/IN6 | Differential clock inputs | Accept 5–710 MHz AC-coupled differential reference; require external 100 Ω termination |
| IN3/IN4 | Single-ended clock inputs | Support CMOS/SSTL/HSTL inputs from 5–350 MHz; DC-coupled with 1.8/2.5/3.3 V logic levels |
| CLK0A/CLK0B – CLK3A/CLK3B | Differential clock outputs | Four independent output pairs; each configurable as LVPECL, LVDS, HCSL, CML, SSTL, or HSTL |
| VDDO0–VDDO3 | Output buffer supply rails | Separate 1.5/1.8/2.5/3.3 V supplies per output bank; decoupling required per rail |
| VDD | Core supply | 1.8/2.5/3.3 V core power; must be stable within ±10% across –40 to +85 °C |
| OEB | Output enable (active-low) | Hardware-controlled global disable; places all outputs in high-impedance state when asserted |
| LOSLOL | Loss-of-signal/loss-of-lock alarm | Open-drain output asserting low on input clock loss or PLL unlock; requires external pull-up |
| RSVD_GND | Reserved ground | Internally connected to substrate; must be tied to PCB ground plane for EMI and thermal integrity |
Key Features
| Feature | Design Value |
|---|---|
| MultiSynth fractional-N synthesis | Enables any-frequency generation per output with zero ppm error and <0.7 ps RMS jitter - eliminates need for multiple crystals or discrete PLLs |
| Independent output voltage per driver | Each of four output banks (VDDO0–VDDO3) supports 1.5/1.8/2.5/3.3 V, enabling direct interface with mixed-voltage FPGAs, ASICs, and SerDes without level translation |
| Pin-controlled phase adjustment | ±45 ns phase offset per output in 20 ps steps via PINC/FINC pins - allows deterministic skew calibration between SerDes lanes or memory channels |
| PCIe 2.0-compliant spread spectrum | SSC available on any 100 MHz output with Rn = 1; reduces EMI peak emissions by >10 dB without affecting link compliance |
| Factory-programmed configuration | No I²C or software initialization required; boots into pre-defined frequency/phase/format settings - simplifies boot-time timing in embedded systems |
| Zero-delay mode support | Optional external feedback path (FDBK/FDBKB) enables phase-aligned output-to-input tracking - critical for jitter-sensitive repeater and retimer applications |
Applications
| Ethernet Switch Timing | PCIe 3.0 Root Complex Clocking |
|---|---|
Use Scenario: High-density 10/25/100 GbE switch fabric requiring synchronized clocks across multiple PHYs, MACs, and packet buffers. IC Role / Device Role / Timing Role: Quad-output clock generator providing four independent, low-jitter clocks (125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz) to separate switch ASIC domains. Use Value: 0.7 ps RMS jitter ensures sub-UI timing margin for 25+ Gbps NRZ links; pin-controlled phase alignment eliminates inter-lane skew in multi-port designs. |
Use Scenario: Server motherboard with dual CPU sockets and multiple PCIe 3.0 x16 slots requiring common-clock architecture with strict jitter limits. IC Role / Device Role / Timing Role: Primary clock source delivering 100 MHz PCIe reference to root complex, switch, and endpoint devices with SSC enabled on designated outputs. Use Value: Meets PCIe 3.0 common clock TJ < 3.0 ps pk-pk requirement; factory-programmed configuration guarantees deterministic startup without BIOS intervention. |
| Broadcast Video Synchronization | FPGA-Based Test Equipment |
Use Scenario: SMPTE ST 2082-1 (12G-SDI) video processing platform needing genlock-capable, low-phase-noise clocks for ADC/DAC sampling and frame sync. IC Role / Device Role / Timing Role: Any-frequency synthesizer generating 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz simultaneously from a single 27 MHz crystal reference. Use Value: –126 dBc/Hz @ 10 kHz phase noise enables clean analog video reconstruction; independent output voltage rails match varying DAC/ADC supply requirements. |
Use Scenario: High-speed digital pattern generator using Xilinx Kintex Ultrascale+ FPGA, requiring precise clock domain crossing and multi-rate stimulus generation. IC Role / Device Role / Timing Role: Configurable clock hub supplying 100 MHz system clock, 200 MHz DDR4 PHY clock, 300 MHz test pattern clock, and 400 MHz ADC sampling clock - all from one device. Use Value: Frequency increment/decrement on CLK0A/B enables real-time margin testing of setup/hold timing; 20 ps phase step resolution supports fine-grained delay calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si5332A-D06018-GM | Higher integration: includes integrated crystal oscillator (XO), eliminating external crystal; same MultiSynth engine and pinout-compatible | Reduces BOM count and board space; preferred for space-constrained designs where crystal layout sensitivity is a concern | Select when crystal placement or EMI from crystal traces is problematic; note higher cost and fixed XO frequency tolerance vs. external crystal flexibility |
| ICS853S01AGI-01LFT | Fixed-frequency, non-synthesizing quad LVDS generator; no fractional-N capability; max 250 MHz output; no phase/frequency tuning | Suitable only for static clock trees with known, unchanging frequencies; lacks any-frequency synthesis or dynamic adjustment | Choose only for legacy designs requiring drop-in replacement of older IDT clock generators with identical pinout and no firmware changes |
Compared with SI5334M-B06018-GMR, Si5332A-D06018-GM adds integrated crystal convenience but sacrifices external reference flexibility, while ICS853S01AGI-01LFT offers lower cost and simpler validation at the expense of frequency agility and jitter performance - making SI5334M-B06018-GMR optimal for next-gen adaptive timing architectures.
Availability
SI5334M-B06018-GMR is available at Aetrix Electronics and suitable for Ethernet switch/router timing, PCIe 3.0 root complex clocking, and broadcast video synchronization requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SI5334M-B06018-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for infrastructure, automotive, and mobile markets.
The Si5334 product line delivers pin-configurable, low-jitter clock generation for high-speed serial interfaces including PCIe, Ethernet, Fibre Channel, and broadcast video - designed to replace discrete crystal oscillators and simplify timing architecture in multi-protocol systems.
FAQ
What is the factory-programmed configuration of SI5334M-B06018-GMR?
The SI5334M-B06018-GMR is factory-programmed with a specific frequency plan, output format (LVDS), voltage rails (VDDO0–VDDO3 = 2.5 V), and pin-control logic enabling immediate operation at power-up without I²C initialization. Its configuration matches the "B06018" variant designation in Skyworks' ordering matrix, supporting four independent outputs optimized for telecom and datacom timing applications. SI5334M-B06018-GMR does not require external programming to function.
Does SI5334M-B06018-GMR support PCIe 3.0 jitter compliance?
Yes, SI5334M-B06018-GMR meets PCIe 3.0 common clock total jitter requirements with 0.15–0.45 ps RMS jitter (10 kHz–50 MHz) when configured for 100 MHz HCSL outputs. Measured jitter data is validated per Intel Clock Jitter Tool v1.6.4 and AN562 methodology. SI5334M-B06018-GMR achieves this using its MultiSynth fractional-N synthesis and low-noise VCO architecture - no additional filtering or external components are needed.
Can SI5334M-B06018-GMR generate different output frequencies simultaneously?
Yes, SI5334M-B06018-GMR supports fully independent frequency synthesis on all four differential outputs: each CLKnA/B pair can be set to a unique frequency from 0.16 MHz to 710 MHz (subject to VCO and divider constraints). For example, it can deliver 125 MHz to a switch ASIC, 156.25 MHz to a PHY, 312.5 MHz to a SerDes block, and 625 MHz to an FPGA transceiver - all simultaneously and with zero ppm error. SI5334M-B06018-GMR uses four dedicated MultiSynth dividers to achieve this.
What is the role of the LOSLOL pin on SI5334M-B06018-GMR?
The LOSLOL pin on SI5334M-B06018-GMR is an open-drain alarm output that asserts low under two conditions: loss of input clock signal (within 2.6–5 µs) or loss of PLL lock (within 5–10 ms). It serves as a hardware fault indicator for system monitoring and fail-safe shutdown logic. An external pull-up resistor is required, and the pin is electrically isolated from internal logic to prevent backdrive. SI5334M-B06018-GMR uses this pin to enable autonomous system recovery without processor intervention.
Is SI5334M-B06018-GMR compatible with 1.8 V core supply operation?
Yes, SI5334M-B06018-GMR supports 1.8 V core supply operation across the full industrial temperature range (–40 °C to +85 °C), with VDD specified from 1.71 V to 1.98 V (–5% to +10%). Core current draw is 45 mA typical at 100 MHz output with 25 MHz reference. SI5334M-B06018-GMR maintains full specification compliance - including jitter, phase noise, and output drive strength - at 1.8 V, enabling low-power system designs without performance trade-offs.
SI5334M-B06018-GMR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- -
- Package/Case:
- 24-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- PLL:
- -
- Main Purpose:
- -
- Input:
- -
- Output:
- -
- Number of Circuits:
- -
- Ratio - Input:Output:
- -
- Differential - Input:Output:
- -
- Frequency - Max:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 24-QFN (4x4)
SI5334M-B06018-GMR FAQ
1.How can I place an order for SI5334M-B06018-GMR through Aetrix?
Please submit a Request for Quotation (RFQ) for SI5334M-B06018-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SI5334M-B06018-GMR reliable?
The price and inventory of SI5334M-B06018-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334M-B06018-GMR is usually 5 days.
3.What payment methods are accepted for SI5334M-B06018-GMR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334M-B06018-GMR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SI5334M-B06018-GMR?
SI5334M-B06018-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SI5334M-B06018-GMR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SI5334M-B06018-GMR?
For technical support, including SI5334M-B06018-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334M-B06018-GMR requirements.
6.How does Aetrix verify that SI5334M-B06018-GMR is sourced from the original manufacturer or authorized distributors?
All SI5334M-B06018-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334M-B06018-GMR meets industry standards.
7.What is the process for return or replacement of SI5334M-B06018-GMR?
All SI5334M-B06018-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5334M-B06018-GMR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SI5334M-B06018-GMR part is unused and in its original packaging.
Return procedure for SI5334M-B06018-GMR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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