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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Application Specific Clock/Timing

Skyworks Solutions Inc. SI5334M-B06024-GMR

Name: SI5334M-B06024-GMR
Brand: Skyworks Solutions Inc.
SKU: SI5334M-B06024-GMR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SI5334M-B06024-GMR

Manufacturer:: Skyworks Solutions Inc.

Category:: Application Specific Clock/Timing

Package:: 24-VFQFN Exposed Pad

Datasheet:: SI5334M-B06024-GMR.pdf

Description:: 4-OUTPUT, ANY FREQUENCY(<200MHZ)

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SI5334M-B06024-GMR from Skyworks Solutions is a pin-controlled, any-frequency quad clock generator with four independently configurable differential outputs. It synthesizes frequencies from 0.16 MHz to 710 MHz using MultiSynth technology, delivers 0.7 ps RMS typical phase jitter, supports LVPECL/LVDS/HCSL/CMOS/SSTL/HSTL output formats, and operates from 1.8/2.5/3.3 V core supply - deployed in PCIe 3.0 timing, FPGA clocking, and broadcast video systems.

For engineers reviewing the SI5334M-B06024-GMR datasheet, SI5334M-B06024-GMR pinout, SI5334M-B06024-GMR application, or SI5334M-B06024-GMR equivalent, key selection considerations include its 24-QFN package, factory-programmed configuration, independent output voltage per driver (1.5–3.3 V), zero-ppm frequency accuracy, and support for glitchless 1 ppm frequency increment/decrement on CLK0A/B.

Technical Context

The SI5334M-B06024-GMR integrates a fractional-N PLL with on-chip VCO and four independent MultiSynth synthesis stages, each feeding one of four differential output drivers. Its architecture enables integer and fractional frequency synthesis up to 710 MHz while maintaining sub-1 ps RMS jitter through low-noise charge pump design and optimized loop filter integration.

Input flexibility includes crystal (8–30 MHz), CMOS (5–200 MHz), SSTL/HSTL (5–350 MHz), or differential (5–710 MHz) references. Output drivers support format and voltage independence per channel, with programmable initial phase offset (±45 ns), <20 ps phase step resolution, and optional PCIe-compliant spread spectrum on 100 MHz outputs.

Key Specifications

Parameter	Value and Actual Design Meaning
Output count & type	4 differential clock outputs, each independently configurable - enables multi-domain clocking without external fanout buffers
Frequency range	0.16–350 MHz (all outputs); select frequencies up to 710 MHz - covers PCIe Gen3 (100 MHz), Ethernet (125/156.25 MHz), and Fibre Channel (1.0625 GHz × 1/3)
Phase jitter (RMS)	0.7 ps typical (12 kHz–20 MHz) - meets stringent PCI Express 3.0 and 10GbE jitter requirements
Core supply	1.8 V / 2.5 V / 3.3 V - supports mixed-voltage system integration and low-power operation (45 mA typ)
Output formats	LVPECL, LVDS, HCSL, CMOS, SSTL, HSTL - allows direct interface to FPGAs, processors, SerDes, and memory interfaces
Package	24-pin QFN, 4 mm × 4 mm - space-constrained PCB layout compatible with high-density routing
Operating temp	–40 °C to +85 °C - qualified for industrial and telecom line card environments

Pinout & Package

SI5334M-B06024-GMR is housed in a 24-lead, 4 mm × 4 mm QFN package with exposed thermal pad. Pin assignments are fixed per Skyworks Si5334 family specification and support pin-strapped configuration without I²C.

Pin/Terminal	Circuit Role	Design Meaning
CLK0A / CLK0B	Differential output pair 0	Primary configurable clock output; supports frequency increment/decrement (1 ppm steps) and phase adjustment (±45 ns)
CLK1A / CLK1B	Differential output pair 1	Independent synthesis path; format and voltage selectable per driver - enables dual-domain clocking (e.g., CPU + DDR)
CLK2A / CLK2B	Differential output pair 2	Configurable output with same MultiSynth flexibility as CLK0/CLK1 - used for PCIe reference + SerDes lane clocks
CLK3A / CLK3B	Differential output pair 3	Fourth independent clock domain; supports HCSL for PCIe Gen2/3 or LVDS for FPGA transceivers
IN1 / IN2	Differential reference input	Accepts 5–710 MHz differential clock; internal 100 Ω termination - eliminates need for external AC-coupling resistors
IN3 / IN4	Single-ended reference input	Supports CMOS/SSTL/HSTL inputs (5–350 MHz); 20 kΩ internal pull-up/down - simplifies crystal oscillator or buffer interface
VDDO0–VDDO3	Output buffer supplies	Independent 1.5/1.8/2.5/3.3 V per output bank - enables mixed-signal SoC interfacing without level shifters
VDD	Core supply	1.8/2.5/3.3 V core rail; decoupling required per datasheet layout guidelines to maintain jitter performance
LOSLOL	Loss-of-signal/loss-of-lock alarm	Open-drain output asserting within 5 µs of input failure or PLL unlock - enables system-level fault monitoring
OEB	Output enable bar	Active-low global output disable; synchronously gates all four outputs - supports power-aware clock gating
RSVD_GND	Reserved ground	Internally connected to die substrate; must be tied to PCB ground plane - critical for thermal and noise integrity

Key Features

Feature	Design Value
MultiSynth synthesis per output	Enables independent, any-frequency generation (0.16–710 MHz) with zero ppm error - eliminates need for multiple discrete oscillators
Per-output voltage control	Each VDDOx pin supports 1.5/1.8/2.5/3.3 V - allows direct connection to diverse logic families (e.g., 1.8 V FPGA I/O + 3.3 V PHY)
Glitchless frequency tuning	1 ppm step size on CLK0A/B with no output interruption - supports real-time margin testing and dynamic frequency scaling
Sub-20 ps phase resolution	Adjustable phase offset from –45 to +45 ns in <20 ps increments - enables precise skew alignment across high-speed SerDes lanes
PCIe 2.0-compliant SSC	Spread spectrum available on any 100 MHz output with 0.5% deviation at 30–33 kHz - reduces EMI without affecting timing compliance

Applications

PCI Express Timing	FPGA & Processor Clocking
Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen3 slots in a server backplane. IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew. Use Value: Eliminates inter-slot timing skew; meets PCIe 3.0 ±300 ps total jitter requirement at 100 MHz with 0.7 ps RMS phase jitter.	Use Scenario: Supplying distinct clock domains to an FPGA fabric (156.25 MHz), transceivers (125 MHz), DDR4 controller (400 MHz), and ARM processor (500 MHz). IC Role / Device Role / Timing Role: Single-chip, multi-frequency clock source replacing discrete oscillators and fanout buffers. Use Value: Reduces BOM count by 4×; supports per-domain voltage (1.8 V for FPGA I/O, 2.5 V for DDR4) without level shifters.
Broadcast Video/Audio Sync	Telecom Line Cards
Use Scenario: Generating SMPTE 2082 (270 MHz), AES11 (48 kHz), and HD-SDI pixel clocks (74.25 MHz) from a single 27 MHz crystal. IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with ultra-low jitter for broadcast-grade timing distribution. Use Value: Achieves <1 ps RMS jitter at 270 MHz - preserves eye diagram integrity and prevents frame sync errors in 4K/8K workflows.	Use Scenario: Clocking multiple DSPs, ADCs, and SerDes on a 10G line card requiring OC-12 (155.52 MHz), SONET, and Ethernet (125 MHz) references. IC Role / Device Role / Timing Role: High-reliability, temperature-stable clock generator for carrier-grade infrastructure. Use Value: Maintains 0.7 ps RMS jitter across –40 °C to +85 °C; supports loss-of-lock detection for OAM alerting.

PCI Express Timing

FPGA & Processor Clocking

Use Scenario: Providing synchronized 100 MHz reference clocks to multiple PCIe Gen3 slots in a server backplane.

IC Role / Device Role / Timing Role: Quad-output clock generator delivering four independent, low-jitter PCIe-compliant clocks with matched skew.

Use Value: Eliminates inter-slot timing skew; meets PCIe 3.0 ±300 ps total jitter requirement at 100 MHz with 0.7 ps RMS phase jitter.

Use Scenario: Supplying distinct clock domains to an FPGA fabric (156.25 MHz), transceivers (125 MHz), DDR4 controller (400 MHz), and ARM processor (500 MHz).

IC Role / Device Role / Timing Role: Single-chip, multi-frequency clock source replacing discrete oscillators and fanout buffers.

Use Value: Reduces BOM count by 4×; supports per-domain voltage (1.8 V for FPGA I/O, 2.5 V for DDR4) without level shifters.

Broadcast Video/Audio Sync

Telecom Line Cards

Use Scenario: Generating SMPTE 2082 (270 MHz), AES11 (48 kHz), and HD-SDI pixel clocks (74.25 MHz) from a single 27 MHz crystal.

IC Role / Device Role / Timing Role: Any-frequency clock synthesizer with ultra-low jitter for broadcast-grade timing distribution.

Use Value: Achieves <1 ps RMS jitter at 270 MHz - preserves eye diagram integrity and prevents frame sync errors in 4K/8K workflows.

Use Scenario: Clocking multiple DSPs, ADCs, and SerDes on a 10G line card requiring OC-12 (155.52 MHz), SONET, and Ethernet (125 MHz) references.

IC Role / Device Role / Timing Role: High-reliability, temperature-stable clock generator for carrier-grade infrastructure.

Use Value: Maintains 0.7 ps RMS jitter across –40 °C to +85 °C; supports loss-of-lock detection for OAM alerting.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D06024-GM	Higher integration: integrated EEPROM, I²C programmability, and enhanced jitter filtering (0.5 ps RMS typical)	Requires firmware initialization; not pin-compatible - needs PCB redesign and software support	Select when field reconfiguration or tighter jitter specs are required; avoid for drop-in replacement
ICS854S01AGI-01LFT	Fixed-frequency quad LVDS generator (100/125/156.25/200 MHz); no frequency synthesis or voltage flexibility	Limited to pre-defined frequencies; no crystal input or phase adjustment - suitable only for static clock trees	Choose only for cost-sensitive, fixed-frequency applications where MultiSynth flexibility is unnecessary

Compared with Si5332A-D06024-GM and ICS854S01AGI-01LFT, SI5334M-B06024-GMR provides factory-programmed, pin-controlled operation with full frequency agility and per-output voltage control - making it optimal for designs needing guaranteed startup behavior, minimal firmware dependency, and mixed-voltage timing domains.

Availability

SI5334M-B06024-GMR is available at Aetrix Electronics and suitable for PCIe 3.0 timing, FPGA clocking, and broadcast video systems requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.

Supply support for SI5334M-B06024-GMR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog components for communications, automotive, and industrial markets.

The Si5334 product line delivers pin-configurable, any-frequency clock generation for high-speed digital systems - designed to replace multiple discrete oscillators and simplify timing architecture in servers, networking gear, and broadcast equipment.

FAQ

What is the maximum output frequency supported by SI5334M-B06024-GMR?

The SI5334M-B06024-GMR supports output frequencies up to 350 MHz on all four differential outputs using standard MultiSynth synthesis. For select configurations, it can generate frequencies up to 710 MHz - specifically when operating in higher-VCO modes with appropriate R-divider settings. This capability enables direct support for PCIe Gen3 (100 MHz), 10GbE (156.25 MHz), and Fibre Channel (1.0625 GHz × 1/3 = 354.167 MHz, rounded to supported 350 MHz limit).

Does SI5334M-B06024-GMR require external programming or configuration after power-up?

No, SI5334M-B06024-GMR does not require external programming or configuration after power-up. It is factory-programmed with a fixed configuration stored in one-time-programmable (OTP) memory. Upon power application, the device begins operation immediately in its predefined state - supporting deterministic startup without I²C host intervention or firmware initialization. This makes SI5334M-B06024-GMR ideal for systems requiring guaranteed boot-time clock availability.

Can SI5334M-B06024-GMR generate different output formats simultaneously?

Yes, SI5334M-B06024-GMR supports simultaneous use of different output formats across its four differential pairs. Each output (CLK0A/B through CLK3A/B) can be independently configured for LVPECL, LVDS, HCSL, CMOS, SSTL, or HSTL. This allows, for example, LVDS for FPGA transceivers, HCSL for PCIe slots, and CMOS for microcontroller peripherals - all from a single SI5334M-B06024-GMR device without external level-shifting circuitry.

What is the function of the LOSLOL pin on SI5334M-B06024-GMR?

The LOSLOL pin on SI5334M-B06024-GMR is an open-drain output that asserts low within 5 µs upon detection of either loss-of-signal (on any input clock) or loss-of-lock (PLL unlock). It deasserts within 0.2–1 µs after signal recovery or lock reacquisition. This pin provides hardware-level fault signaling to system supervisors or watchdog circuits - enabling rapid diagnostics and failover response without software polling, which is critical in telecom and industrial safety-critical applications.

Is SI5334M-B06024-GMR compatible with crystal inputs?

Yes, SI5334M-B06024-GMR accepts crystal inputs from 8 MHz to 30 MHz directly on the IN1/IN2 pins. The device includes on-chip load capacitance (11–13 pF supported, 17–19 pF recommended) and crystal drive level control (max 100 µW), eliminating the need for external capacitors or buffer amplifiers. This enables compact, low-component-count clock solutions - particularly valuable in space-constrained applications like pluggable optical modules and edge compute devices.

SI5334M-B06024-GMR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

PLL:: -

Main Purpose:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-QFN (4x4)

SI5334M-B06024-GMR FAQ

1.How can I place an order for SI5334M-B06024-GMR through Aetrix?

Please submit a Request for Quotation (RFQ) for SI5334M-B06024-GMR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SI5334M-B06024-GMR reliable?

The price and inventory of SI5334M-B06024-GMR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SI5334M-B06024-GMR is usually 5 days.

3.What payment methods are accepted for SI5334M-B06024-GMR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SI5334M-B06024-GMR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SI5334M-B06024-GMR?

SI5334M-B06024-GMR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SI5334M-B06024-GMR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SI5334M-B06024-GMR?

For technical support, including SI5334M-B06024-GMR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SI5334M-B06024-GMR requirements.

6.How does Aetrix verify that SI5334M-B06024-GMR is sourced from the original manufacturer or authorized distributors?

All SI5334M-B06024-GMR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SI5334M-B06024-GMR meets industry standards.

7.What is the process for return or replacement of SI5334M-B06024-GMR?

All SI5334M-B06024-GMR units undergo pre-shipment inspection (PSI). If there is an issue with SI5334M-B06024-GMR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SI5334M-B06024-GMR part is unused and in its original packaging.

Return procedure for SI5334M-B06024-GMR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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